Motorola MVME1X7P - Manual (Page 304)

Index
IN-2 Computer Group Literature Center Web Site
I
N
D
E
X
B
Back Off signal (PCCchip2 ASIC) 3-5
backward compatibility 1-2
base address, VMEchip2 LCSR 2-20
battery backup 1-10
BBRAM
configuration area memory map 1-42
interface, PCCchip2 3-3
memory map 1-41
speed control 3-15
BBRAM (battery-backed-up RAM) 1-12
restoring lost Ethernet address 1-15
BBSY* signal, VMEbus 2-98
BERR* signal, VMEbus 2-17
BGIN filters, VMEbus 2-98
binary number, symbol for xxiii
block (D64) access cycles, VMEbus 2-33 ,
2-36
block access cycles, VMEbus 2-33 , 2-36
block diagrams
MVME1X7P board 1-4
PCCchip2 ASIC 3-2
VMEchip2 ASIC 2-5
block transfer
cycles, VMEchip2 DMAC 2-11
mode 2-9
modes, DMAC 2-59
board
address, GCSR 2-48
failure signal, VMEchip2 ASIC 2-70
ID 1-44
serial number 1-44
speed 1-46
status/control register, VMEchip2 2-106
Board Control register, VMEchip2 2-101
BRDFAIL* signal pin, VMEchip2 ASIC
2-70 , 2-71
broadcast interrupt function (VMEchip2
timers) 2-15
broadcast mode, VMEbus 2-16
BSY signal and arbitration timer 2-17
burst read cycle type 4-5
burst write cycle type 4-6
bus error 3-4
processing 1-55
sources 1-54
status, SCSI 3-37
bus map decoder, LCSR 2-20
bus sizing, VMEchip2 ASIC 2-6
bus timer (local) 1-17
bus timer enable/disable, VMEbus 2-17
bus timers, example of use 1-51
byte counter, DMAC 2-60
C
cache coherency
MCECC sector 4-4
MVME1x7P 1-49
cache inhibit function 1-20
cautions for use of reset (VMEchip2) 2-101
CD2401 serial controller chip 1-12 , 3-7
memory map 1-36
changes from previous boards A-1
checksum byte 1-46
chip arbiter, VMEbus 2-17
chip ID and revision registers (VMEchip2
ASIC) 2-100
Chip ID register
MCECC sector 4-13
PCCchip2 ASIC 3-14
Chip Revision register
MCECC sector 4-13
PCCchip2 ASIC 3-14
Chip Speed register (PCCchip2 ASIC) 3-46
clear bits
LANC error 3-34
SCSI error 3-37
clear overflow counter
tick timer 1 3-23
tick timer 2 3-22
clear-on-compare
tick timer 1 3-23
tick timer 2 3-22