Motorola MVME1X7P - Manual (Page 210)

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PCCchip2
3
Table 3-2. PCCchip2 Memory Map - Control and Status Registers
This sheet continues on facing page.
PRTR
FLT
PLTY
PRTR
FLT
E/L*
PRTR
FLT
INT
PRTR
FLT
IEN
PRTR
FLT
ICLR
PRTR FAULT
IRQ LEVEL
PRTR
ACK
PLTY
PRTR
ACK
E/L*
PRTR
ACK
INT
PRTR
ACK
IEN
PRTR
ACK
ICLR
SCC
RTRY
ERR
PCCchip2 Base Address = $FFF42000
OFFSET:
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
PRTR ACK
IRQ LEVEL
GPI
PLTY
D16 D23 D24 D31
CHIP ID CHIP REVISION
TIC TIMER 1
TIC TIMER 1
TIC TIMER 2
TIC TIMER 2
PRESCALER COUNT REGISTER PRESCALER CLOCK ADJUST
GPI
E/L*
GPI
INT GPI
IEN GPI
ICLR
GPI
IRQ LEVEL
GPI GPOE GPO
SCC
PAR
ERR SCC
EXT
ERR
SCC
LTO
ERR
SCC
SCLR
SCC
MDM
ERR
SCC
MDM
IEN
SCC
MDM
AVEC
SCC MODEM
IRQ LEVEL
SCC TRANSMIT PIACK
LAN
PAR
ERR
LAN
EXT
ERR
LAN
LTO
ERR
LAN
SCLR
SCSI
PAR
ERR
SCSI
EXT
ERR
SCSI
LTO
ERR
SCSI
SCLR
PRTR
BSY
PLTY
PRTR
BSY
E/L*
PRTR
BSY
INT
PRTR
BSY
IEN
PRTR
BSY
ICLR
PRTR BSY
IRQ LEVEL
CHIP SPEED
SCC PROVIDES ITS OWN VECTORS