Motorola MVME1X7P - Manual (Page 22)

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Overview of Contents
Chapter 1, Programming Issues , describes the board-level hardware
features of MVME1X7P single-board computers. It includes memory
maps and a discussion of some general software considerations such as
cache coherency, interrupts, and bus errors.
Chapter 2, VMEchip2 , describes the VMEchip2 ASIC, the local
bus/VMEbus interface chip on MVME1X7P boards.
Chapter 3, PCCchip2 , describes the PCCchip2 ASIC. The PCChip2 is a
peripheral channel controller designed to interface an MC680x0-
compatible local bus to various on-board peripheral devices such as SCSI
and LAN controllers.
Chapter 4, MCECC Functions , describes the ECC DRAM controller ASIC
(MCECC). On the MVME1X7P boards, it supplies the interface to a 144-
bit wide DRAM memory system.
Appendix A, Summary of Changes , lists the modifications that
accompanied the introduction of the Petra ASIC on the MVME167P and
MVME177P.
Appendix B, Printer and Serial Port Connections , contains drawings of
the printer and serial port interface connections available with the
MVME167P/MVME177P and MVME712 series transition board.
Appendix C, Related Documentation , lists all documentation related to the
MVME167P and MVME177P.
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