Motorola MVME1X7P - Manual (Page 199)

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3 PCCchip2
Introduction
This chapter defines the peripheral channel controller ASIC, referred to
hereafter as the PCCchip2. The PCCchip2 is designed to interface an
MC68040-compatible local bus (Local Bus) to various peripheral devices.
Summary of Major Features
This section lists the major features of the PCCchip2.
❏ BBRAM interface with dynamic sizing support.
❏ 8-bit parallel I/O port.
❏ Master and slave interface for CD2401 Intelligent Multi-Protocol
Peripheral.
❏ Host interface to Intel 82596CA LAN Coprocessor.
❏ Host interface to NCR SCSI I/O Processor.
❏ Two 32-bit tick timers.
❏ Interrupt handler for tick timers and all peripherals:
– All interrupts are level-programmable.
– All interrupts are maskable.
– All interrupts provide a unique vector.