Motorola MVME1X7P - Manual (Page 153)

LCSR Programming Model
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DMAIC The DMAC interrupt counter is incremented when an
interrupt is sent to the local bus interrupter. The value in
this counter indicates the number of commands processed
when the DMAC is operated in command chaining mode.
If the interrupt count exceeds 15, the counter rolls over.
This counter operates regardless of whether the DMAC
interrupts are enabled. This counter is cleared when the
DMAC is enabled.
DMAC Status Register
This is the DMAC status register.
DONE This bit is set when the DMAC has finished executing
commands, either without errors or because the halt bit
was set. This bit is cleared when the DMAC is enabled.
VME If this bit is set, the DMAC has received a VMEbus BERR
during a data transfer. This bit is cleared when the DMAC
is enabled.
TBL If this bit is set, the DMAC has received an error on the
local bus while it was reading commands from the
command packet. Additional information is provided in
bits 3 - 6 (DLTO, DLOB, DLPE, and DLBE). This bit is
cleared when the DMAC is enabled.
DLTO If this bit is set, the DMAC has received a TEA and the
status indicated a local bus time-out. This bit is cleared
when the DMAC is enabled.
DLOB If this bit is set, the DMAC has received a TEA and the
status indicated off-board. This bit is cleared when the
DMAC is enabled.
ADR/SIZ $FFF40048 (8 bits of 32)
BIT 7 6 5 4 3 2 1 0
NAME MLTO DLBE DLPE DLOB DLTO TBL VME DONE
OPER R R R R R R R R
RESET 0 PS 0 PS 0 PS 0 PS 0 PS 0 PS 0 PS 0 PS