Motorola MVME1X7P - Manual (Page 162)

2-72 Computer Group Literature Center Web Site
VMEchip2
2
WDCS When this bit is set high, the watchdog time-out status bit
(WDTO bit in this register) is cleared.
SRST When this bit is set high, a SYSRESET signal is generated
on the VMEbus. SYSRESET resets the VMEchip2 and
clears this bit.
Tick Timer 2 Control Register
EN When this bit is high, the counter increments. When this
bit is low, the counter does not increment.
COC When this bit is high, the counter is reset to 0 when it
compares with the compare register. When this bit is low,
the counter is not reset.
COVF The overflow counter is cleared when a 1 is written to this
bit.
OVF These bits are the output of the overflow counter. The
overflow counter is incremented each time the tick timer
sends an interrupt to the local bus interrupter. The
overflow counter can be cleared by writing a 1 to the
COVF bit.
ADR/SIZ $FFF40060 (8 bits [7 used] of 32)
BIT 15 14 13 12 11 10 9 8
NAME OVF COVF COC EN
OPER R C R/W R/W
RESET 0 PS 0 PS 0 PS 0 PS