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Motorola DSP96002 User Manual

Page 894

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Index (Continued)

MOTOROLA

INDEX - 7

Port B Control Register (PBC)

. . . . . . 4-6

Port B Data Direction Register

. . . . . . 4-6

Port B Data Register

. . . . . . . . . . . . . . 4-6

Port C

. . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Port C Control Register

. . . . . . . . . . . . 4-6

Port C Data Direction Register

. . . . . . 4-6

Port C Data Register

. . . . . . . . . . . . . . 4-6

Port C Data Register (PCD)

. . . . . . . . 4-6

Port Registers

. . . . . . . . . . . . . . . . . . . 4-4

Programming Models

. . . . . . . . . . . . . 5-5

—R—

Real-Time I/O Example with On-Chip Co-

dec and PLL

. . . . . . . . . . . . . . 6-62

Receive Byte Registers

. . . . . . . . . 5-5

,

57

Receive Data Register (CRX)

. . . . . . . .50

Receive Slot Mask Registers

. . . . . . 8-23

Receive Slot Mask Shift Register

. . . 8-24

Reference Voltage Generator

. . . . . . . 6-3

Register Transfer Conditional Move In-

struction

. . . . . . . . . . . . . . . . . . .38

Register Transfer without Parallel Move In-

struction

. . . . . . . . . . . . . . . . . . .37

REP and DO Instructions

. . . . . . . . . . .35

Reset Circuit

. . . . . . . . . . . . . . . . . . . . .23

Reverse Carry

. . . . . . . . . . . . . . . . . . . 1-9

—S—

Serial Clock

. . . . . . . . . . . . . . . . . . . . . 8-7

Serial Control

. . . . . . . . . . . . . . . .8-7

,

8-8

Serial Receive Data Pin

. . . . . . . . . . . 8-7

Serial Transmit Data Pin

. . . . . . . . . . . 8-7

Short Immediate Move Instructions

. . .36

Special Instructions

. . . . . . . . . . . . . . . .41

SSI Control Register (PCC)

. . . . . . . . .58

SSI Control Register A (CRA)

. . . . . . . .61

SSI Control Register B (CRB)

. . . . . . . .61

SSI Receive Slot Mask

. . . . . . . . . . . . .59

SSI Serial Receive Register

. . . . . . . . .58

SSI Serial Transmit Register

. . . . . . . . .58

SSI Status Register (SSISR)

. . . . . . . .62

SSI Transmit Slot Mask

. . . . . . . . . . . .60

SSI0 Clock and Frame Sync Generation

.

8-4

SSI0 Clock Generator

. . . . . . . . . . . 8-15

SSI0 Control Register A

. . . . . . . . . . 8-12

SSI0 Control Register B

. . . . . . . . . . 8-15

SSI0 Data and Control Pins

. . . . . . . . 8-4

SSI0 Interface Programming Model

. . 8-9

SSI0 Operating Modes

. . . . . . . . 8-3

,

8-24

SSI0 Receive Data Register

. . . . . . 8-12

SSI0 Receive Shift Register

. . . . . . . 8-12

SSI0 Reset

. . . . . . . . . . . . . . . . . . . . . 8-9

SSI0 Reset and Initialization Procedure

8-

8

SSI0 Status Register

. . . . . . . . . . . . 8-19

SSI0 Transmit Data Register

. . . . . . 8-12

SSI0 Transmit Shift Register

. . . . . . 8-10

SSISR Receive Data Register Full (RDF)

Bit 7

. . . . . . . . . . . . . . . . . . . . 8-22

SSISR Receive Frame Sync (RFS) Bit 3

.

8-20

SSISR Receiver Overrun Error (ROE) Bit 5

. . . . . . . . . . . . . . . . . . . . . . . . 8-21

SSISR Serial Input Flag 1 and 0(IF0, IF1)

Bit 0, 1

. . . . . . . . . . . . . . . . . . 8-20

SSISR Transmit Data Register Empty

(TDE) Bit 6

. . . . . . . . . . . . . . . 8-21

SSISR Transmit Frame Sync (TFS) Bit 2

.

8-20

SSISR Transmitter Underrun Error (TUE)

Bit 4

. . . . . . . . . . . . . . . . . . . . 8-21

Status Register (SR)

. . . . . . . . . . . . . . 42

STOP Instruction

. . . . . . . . . . . . . . . . 9-4

STOP Reset

. . . . . . . . . . . . . . . . . . . . 8-9

Switched Capacitor Filter

. . . . . . . . . . 6-4

System Stack (SS)

. . . . . . . . . . . . . . 1-23

—T—

TCR Inverter Bit (INV) Bit 14

. . . . . . . 7-7

Time Slot Register

. . . . . . . . . . . . . . 8-22

Timer Architecture

. . . . . . . . . . . . . . . 7-3

Timer Compare Register (TCPR)

. 1-17

,

7-

3

,

. . . . . . . . . . . . . . . . . . . . .7-5

,

48

Timer Control Register

. . . . . . . . . . . . 7-3