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Motorola DSP96002 User Manual

Page 819

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MOTOROLA

37

two (CLK/2). During the clock cycle following the point where the counter reaches 0, the

TE

TCR

N

Counter

N

0

N

Interrupt

first

last event

N-1

TIO

new event

2xCLK

N-1

Clock

Figure 11 - Standard Timer Mode, Internal Clock, Output Pulse Enabled (INV=0)

write to

TCR (N) event

(CLK/2)

TE

TCR

write to

N

Counter

Interrupt

first

last event

TIO

new event

2xCLK

Clock

Figure 12 - Standard Timer Mode, Internal Clock, Output Pulse Enabled (INV=1)

TCR(N) event

N

0

N

N-1

N-1

(CLK/2)