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Motorola DSP96002 User Manual

Page 892

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Index (Continued)

MOTOROLA

INDEX - 5

Dual Read Instructions

. . . . . . . . . . . . .32

—E—

Effective Address Update

. . . . . . . . . . .34

Event Select (ES) Bit 8

. . . . . . . . . . . . 7-6

Exception Priorities within an IPL

. . . 1-12

—F—

Fractional Arithmetic

. . . . . . . . . . . . . . 1-8

Frequency Multiplier

. . . . . . . . . . . . . . 9-4

—G—

G Bus Data

. . . . . . . . . . . . . . . . . . . . 1-30

GDB

. . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Global Data Bus

. . . . . . . . . . . . . . . . . 1-7

GSM Bit (GSM)

. . . . . . . . . . . . . . . . . . 9-8

—H—

HCR Host Command Interrupt Enable

(HCIE) Bit 2

. . . . . . . . . . . . . . 5-10

HCR Host Flag 2 (HF2) Bit 3

. . . . . . 5-10

HCR Host Flag 3 (HF3) Bit 4

. . . . . . 5-10

HCR Host Receive Interrupt Enable

(HRIE) Bit 0

. . . . . . . . . . . . . . 5-10

HCR Host Transmit Interrupt Enable

(HTIE) Bit 1

. . . . . . . . . . . . . . 5-10

HCR Reserved Control – Bits 5, 6 and 7

.

5-11

HI

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

Host Control Register

. . . . . . . . . . . . . 5-9

Host Control Register (HCR)

. . . . . . . .53

Host Interface

. . . . . . . . . . . . . . .1-17

,

5-3

Host Port Usage

. . . . . . . . . . . . . . . . 5-21

Host Programmer Considerations

. . . 5-21

Host Receive Data Register

. . . . . . . . 5-6

Host Receive Data Register (HRX)

. . . .54

Host Status Register

. . . . . . . . . . . . . 5-11

Host Status Register (HSR)

. . . . . . . . .54

Host to DSP

. . . . . . . . . . . . . . . . . . . 5-19

Host Transmit Data Register

. . . . . . . . 5-5

Host Transmit Data Register (HTX)

. . . 54

HSR DMA Status (DMA) Bit 7

. . . . . 5-12

HSR Host Command Pending (HCP) Bit 2

. . . . . . . . . . . . . . . . . . . . . . . . 5-11

HSR Host Flag 0 (HF0) Bit 3

. . . . . . 5-12

HSR Host Flag 1 (HF1) Bit 4

. . . . . . 5-12

HSR Host Receive Data Full (HRDF) Bit 0

. . . . . . . . . . . . . . . . . . . . . . . . 5-11

HSR Host Transmit Data Empty (HTDE)

Bit 1

. . . . . . . . . . . . . . . . . . . . 5-11

HSR Reserved Status – Bits 5 and 6

5-12

—I—

I/O Port Set-up

. . . . . . . . . . . . . . . . . . 4-3

ICR Host Flag 0 (HF0) Bit 3

. . . . . . . 5-13

ICR Host Flag 1 (HF1) Bit 4

. . . . . . . 5-14

ICR Host Mode Control (HM1, HM0) Bits 5

and 6

. . . . . . . . . . . . . . . . . . . 5-14

ICR Initialize Bit (INIT) Bit 7

. . . . . . . 5-15

ICR Receive Request Enable (RREQ) Bit 0

. . . . . . . . . . . . . . . . . . . . . . . . 5-12

ICR Transmit Request Enable (TREQ) Bit

1

. . . . . . . . . . . . . . . . . . . . . . 5-13

Instruction Set Summary

. . . . . . . . . . . 29

Integer Data ALU Instructions

. . . . . . . 39

Integer Operations

. . . . . . . . . . . . . . . 1-8

Interrupt Control Register (ICR)

. .5-12

,

55

Interrupt Priority Levels

. . . . . . . . . . 1-12

Interrupt Priority Register (IPR)

. .1-11

,

43

Interrupt Priority Structure

. . . . . . . . 1-12

Interrupt Status Register (ISR)

. . .5-16

,

56

Interrupt Vector Register (IVR)

. . .5-17

,

57

Interrupts Starting Addresses and Sources

. . . . . . . . . . . . . . . . . . . . . . . . . . 28

Inverter Bit (INV) Bit 14

. . . . . . . . . . . 7-7

IPL

. . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

IPR

. . . . . . . . . . . . . . . . . . . . . . . . . 27

,

43

ISR (Reserved Status) Bit 5

. . . . . . . 5-17

ISR DMA Status (DMA) Bit 6

. . . . . . 5-17

ISR Host Flag 2 (HF2) Bit 3

. . . . . . . 5-17

ISR Host Flag 3 (HF3) Bit 4

. . . . . . . 5-17

ISR Host Request (HREQ) Bit 7

. . . 5-17