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Motorola DSP96002 User Manual

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MOTOROLA

DSP96002 USER’S MANUAL

B-171

; *** f = fraction bits, initially bits in mantissas

; *** l = least significant fraction bit, initially in mantissas

; *** g = guard bit

; *** r = round bit

; *** s - sticky bit

; ***

; ***

; *** Routine Inputs:

; *** d6 - IEEE double extended precision operand 1 (destroyed)

; *** d7 - IEEE double extended precision operand 2 (destroyed)

; ***

; *** Routine Outputs:

; *** d5 - IEEE double extended precision result

; ***

; *** Registers Used:

; *** d0.l - general purpose usage

; *** d0.m - unbiased operand 2 exponent

; *** - unbiased result exponent

; *** d0.h - MSB contains the XOR of the sign bits

; *** d1.l - general purpose usage

; *** d1.m - unbiased operand 1 exponent

; *** - loop index for denormalizing upon underflow.

; *** d1.h - LSB contains the sticky bit

; *** d2.m,l - partial product and intermediate calculations

; *** d3.m,l - partial product and intermediate calculations

; *** d4.m,l - partial product and intermediate calculations

; *** d5.m,l - partial product and intermediate calculations

; ***

; *** NOTES: Currently ignores the FR, P, RP bits.

; *** Assumes that operands are NOT UNnormalized numbers

; *** Code size greatly decreased if "depftst" macro

; *** becomes a routine

; ***

section ieeemult

SR_MASK equ $ffff80c0 ; Status Register Mask, resets cond. codes

EXP_MSK equ $7ff ; Mask for exponent field, 16-bits

EBIAS equ $3ff ; Exponent bias for IEEE double precision

EMAX equ $3ff ; Max exp for normalized double precision val

EMIN equ $fffffc02 ; Min exp for normalized double precision val

EDEN equ $fffffc01 ; Exp for denormalized double precision val

MAX equ $7ff ; Max exp (biased), indicating infs & NaNs

SMSK equ $1ff ; Mask for sticky bit calculation

INUM equ $800 ; Increment for LSB

sdptest ; double precision multiplication subroutine

; ****** Define Program Macros ******

depftst macro op,tmp1,tmp2

; This macro performs the "ftst" function on DEP floating pt vars.

; It sets the NAN,I,N,Z bits in the CCR register appropriately.

;

; op = register name of the form "Dn" containing the floating pt var

; in all 96 bits of the register (not destroyed)