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Motorola DSP96002 User Manual

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MOTOROLA

DSP96002 USER’S MANUAL

A - 323

A.9.7 LEA Timing Summary

+ le

MOVEC Operation

Cycles

Comments

Update Addressing Modes

0

Long Displacement

2

Figure A-14 LEA Timing Summary

If there are wait states, (i.e., assumption 4 is not applicable) then to each 1-word instruction timing a "+ap"

term should be added and to each 2-word instruction a "+(2 * ap)" term should be added to account for the

program memory wait states spent to fetch an instruction word to fill the pipeline.

A.9.8 LRA Timing Summary

+ lr

+ lr

LRA Operation

Words

Cycles

PC Relative Long Displacement

1

2

PC Relative Address Reg.

0

0

Figure A-15 LRA Timing Summary

If there are wait states, (i.e., assumption 4 is not applicable) then to each 1-word instruction timing a "+ap"

term should be added and to each 2-word instruction a "+(2 * ap)" term should be added to account for the

program memory wait states spent to fetch an instruction word to fill the pipeline.

A.9.9 Bit Manipulation Timing Summary

Bit Manipulation

+ mvb

Operation

Cycles

Bxxx I/O Short

2 * aio

where Bxxx = BCHG, BCLR or BSET

Bxxx Absolute Short

0

where Bxxx = BCHG, BCLR or BSET

Bxxx Register Direct

0

where Bxxx = BCHG, BCLR or BSET

Bxxx X Memory

ea + (2 * ax)

where Bxxx = BCHG, BCLR or BSET

Bxxx Y Memory

ea + (2 * ay)

where Bxxx = BCHG, BCLR or BSET

BTST I/O Short

aio

BTST Absolute Short

0

BTST Register Direct

0

BTST X Memory

ea + ax

BTST Y Memory

ea + ay

Figure A-16 Bit Manipulation Timing Summary