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Motorola DSP96002 User Manual

Page 192

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A - 4

DSP96002 USER’S MANUAL

MOTOROLA

compare instruction. The

R bit is cleared during processor reset. See the example for

the FCMPG instruction for additional information.

A(Accept)

The A bit is only affected by the compare instructions CMP, CMPG, FCMP and FCMPG.

The A bit is calculated based on its previous value and the results of the current compare

instruction. The A bit is cleared during processor reset. See the example for the FCMPG

instruction for additional information.

There are 16 theoretical combinations of N, Z, I and NAN for floating point results, but only eight combina-

tions are possible in practice due to the exclusive nature of the data types described by the condition

codes. The eight possible combinations are shown in Figure A-3.

Figure A-4 details how each instruction affects the condition codes. Figure A-4 gives the chip implemen-

tation viewpoint while the opcode descriptions in Section A-3 give the user viewpoint. For example, the Z

bit computation for the CLR instruction is shown in the figure as the standard definition while the opcode

description indicates that Z is always set.

N

Z

I

NAN

Result Data Type

0

0

0

0

+Normalized/Denormalized

1

0

0

0

- Normalized/Denormalized

0

1

0

0

+0

1

1

0

0

-0

0

0

1

0

+Infinity

1

0

1

0

-Infinity

0

0

0

1

+NaN

1

0

0

1

-

NaN

Figure A-3.

Possible Combinations of the N, Z, I and NAN Bits for Floating-Point Results