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Fbcc floating-point branch conditionally fbcc – Motorola DSP96002 User Manual

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DSP96002 USER’S MANUAL

MOTOROLA

FBcc

Floating-Point Branch Conditionally

FBcc

Description:

If the specified floating-point condition is true, the address of the instruction immediately following the FB-

Scc instruction and the status register are pushed onto the stack. Program execution then continues at

location PC+displacement. The PC contains the address of the next instruction. If the specified condition

is false, the PC is incremented and program execution continues sequentially. The displacement is a 2’s

complement 32-bit integer that represents the relative distance from the current PC to the destination PC.

Short Displacement, Long Displacement and Address Register PC Relative addressing modes may be

used. The Short Displacement 15-bit data is sign extended to form the PC relative displacement. See

Section A.10 for restrictions. Non-aware floating-point conditions set the SIOP flag in the IER register and

the UNCC bit in the ER register if the NAN bit is set.

"cc" may specify the following conditions:

Non-aware

Mnemonic

Condition

Set UNCC*

EQ

- equal

Z = 1

No

ERR

- error

UNCC v SNAN v OPERR v No
OVF v UNF v DZ = 1

GE

- greater than or equal

NAN v (N & ~Z) = 0

Yes

GL

- greater or less than

NAN v Z = 0

Yes

GLE

- greater, less or equal

NAN = 0

Yes

GT

- greater than

NAN v Z v N = 0

Yes

INF

- infinity

I = 1

Yes

LE

- less than or equal

NAN v ~(N v Z) = 0

Yes

LT

- less than

NAN v Z v ~N = 0

Yes

MI

- minus

N = 1

No

NE(Q) - not equal

Z = 0

No

NGE

- not(greater than or equal)

NAN v (N & ~Z) = 1

Yes

NGL

- not(greater or less than)

NAN v Z = 1

Yes

NGLE - not(greater, less or equal) NAN = 1

Yes

NGT

- not greater than

NAN v Z v N = 1

Yes

NINF

- not infinity

I = 0

Yes

NLE

- not(less than or equal)

NAN v ~(N v Z) = 1

Yes

NLT

- not less than

NAN v Z v ~N = 1

Yes

OR

- ordered

NAN = 0

No

PL

- plus

N = 0

No

UN

- unordered

NAN = 1

No

Note: The operands for the ERR condition are taken from the ER register.
See the description of UNcc in Section A.4.

CCR Condition Codes: Not affected.

Assembler Syntax:

FBcc label (short)

FBcc label

FBcc Rn

Operation:

If cc, then PC+xx

PC

else PC+1

PC

If cc, then PC+xxxx

PC

else PC+1

PC

If cc, then PC+Rn

PC

else PC+1

PC