Motorola DSP96002 - Manual (Page 130)

7 - 44 DSP96002 USER’S MANUAL MOTOROLA
The table in Figure 7-24 shows the data transfers that the DMA Controller is capable of. The number of cy-
cles specified in the Figure 7-24 notes are for the operation of one channel using a continuous block trans-
fer.
DMA data transfers Notes
Int. mem Int. mem (different memory space) #1
Int. mem Int. mem (same memory space) #2
Ext. mem Int. mem (different memory space) #1
Ext. mem Int. mem (same memory space) #2
Ext. mem Ext. mem #3
Int. mem Int. I/O (different memory space) #1
Int. mem Int. I/O (same memory space) #2
Ext. mem Int. I/O (different memory space) #1
Ext. mem Int. I/O (same memory space) #2
Int. I/O Int. I/O #2
Figure 7-24. Direction of DMA Data Transfers
Notes:
1. Two clock cycles for every word.
2. Four clock cycles for every word (the same address bus is used for source and destination).
3. Four clock cycles for every word.