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Bclr bit test and clear bclr – Motorola DSP96002 User Manual

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MOTOROLA

DSP96002 USER’S MANUAL

A - 37

BCLR

Bit Test and Clear

BCLR

Operation:

D{n}

C;

0

D{n}

D{n}

C;

0

D{n}

D{n}

C;

0

D{n}

D{n}

C;

0

D{n}

D{n}

C;

0

D{n}

D{n}

C;

0

D{n}

D{n}

C;

0

D{n}

Assembler Syntax:

BCLR #bit,X: ea

BCLR #bit,X: aa

BCLR #bit,X: pp

BCLR #bit,Y: ea

BCLR #bit,Y: aa

BCLR #bit,Y: pp

BCLR #bit,D

Description:

The nth bit of the destination operand is tested and the state of the nth bit is reflected in the C condition

code bit. After the test, the nth bit is cleared in the destination. All memory alterable addressing modes

may be used. Register, Absolute Short and I/O Short addressing may also be used.

The bit to be tested is selected by an immediate bit number 0-31. This instruction performs a read-modify-

write operation on the destination operand and requires two destination accesses. This instruction pro-

vides a test-and-clear capability which is useful for synchronizing multiple processors using a shared

memory. See Section A.10 for restrictions.

CCR Condition Codes:

For destination operand SR:

C

- Cleared if bit 0 is specified. Not affected otherwise.

V

- Cleared if bit 1 is specified. Not affected otherwise.

Z

- Cleared if bit 2 is specified. Not affected otherwise.

N

- Cleared if bit 3 is specified. Not affected otherwise.

I

- Cleared if bit 4 is specified. Not affected otherwise.

LR

- Cleared if bit 5 is specified. Not affected otherwise.

R

- Cleared if bit 6 is specified. Not affected otherwise.

A

- Cleared if bit 7 is specified. Not affected otherwise.