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Ftrapcc conditional software interrupt ftrapcc – Motorola DSP96002 User Manual

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DSP96002 USER’S MANUAL

MOTOROLA

FTRAPcc Conditional Software Interrupt

FTRAPcc

Operation:

If cc, then begin software exception processing.

Assembler Syntax:

FTRAPcc

Description:

If the specified floating-point condition is true, normal instruction execution is suspended and software ex-

ception processing is initiated. The interrupt priority level (I1,I0) is set to 3 in the status register if a long

interrupt service routine is used. If the specified condition is false, continue with the next instruction. See

Section A.10 for restrictions. Non-aware floating-point conditions set the SIOP flag in the IER register and

the UNCC bit in the ER register if the NAN bit is set. This action occurs before stacking the status register

when the specified non-aware floating-point condition is true.

"cc" may specify the following conditions:

Non-aware

Mnemonic

Condition

Set UNCC*

EQ

- equal

Z = 1

No

ERR

- error

UNCC v SNAN v OPERR v No

OVF v UNF v DZ = 1

GE

- greater than or equal

NAN v (N & ~Z) = 0

Yes

GL

- greater or less than

NAN v Z = 0

Yes

GLE

- greater, less or equal

NAN = 0

Yes

GT

- greater than

NAN v Z v N = 0

Yes

INF

- infinity

I = 1

Yes

LE

- less than or equal

NAN v ~(N v Z) = 0

Yes

LT

- less than

NAN v Z v ~N = 0

Yes

MI

- minus

N = 1

No

NE(Q)

- not equal

Z = 0

No

NGE

- not(greater than or equal)NAN v (N & ~Z) = 1

Yes

NGL

- not(greater or less than) NAN v Z = 1

Yes

NGLE

- not(greater, less or equal)NAN = 1

Yes

NGT

- not greater than

NAN v Z v N = 1

Yes

NINF

- not infinity

I = 0

Yes

NLE

- not(less than or equal)

NAN v ~(N v Z) = 1

Yes

NLT

- not less than

NAN v Z v ~N = 1

Yes

OR

- ordered

NAN = 0

No

PL

- plus

N = 0

No

UN

- unordered

NAN = 1

No

Note: The operands for the ERR condition are taken from the ER register.
* See the description of the UNcc bit in Section A.4.

CCR Condition Codes: Not affected.

ER Status Bits: