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Fclr clear floating-point register fclr – Motorola DSP96002 User Manual

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DSP96002 USER’S MANUAL

MOTOROLA

FCLR

Clear Floating-Point Register

FCLR

10

0000

uu11

0ddd

31

14 13

0

OPTIONAL EFFECTIVE ADDRESS EXTENSION OR IMMEDIATE LONG DATA

DATA BUS MOVE FIELD

Description:

All 96 bits of the destination operand are cleared to zero.

Input Operand(s) Precision: DEP Floating-Point.

Output Operand Precision: DEP Floating-Point.

CCR Condition Codes:

C

- Not affected.

V

- Not affected.

Z

- Always set.

N

- Always cleared.

I

- Always cleared.

LR

- Not affected.

R

- Not affected.

A

- Not affected.

ER Status Bits:

INX

-Always cleared.

DZ

-Always cleared.

UNF

-Always cleared.

OVF

-Always cleared.

OPERR-Always cleared.

SNAN -Not affected.

NAN

-Always cleared.

UNCC -Always cleared.

IER Flags: Not affected.

Instruction Format: FCLR D (move syntax - see the MOVE instruction description.)

Assembler Syntax:

FCLR D (move syntax - see the MOVE instruc-

tion description.)

Operation:

+0

D (parallel data bus move)