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Motorola DSP96002 User Manual

Page 142

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8 - 2

DSP96002 USER’S MANUAL

MOTOROLA

8.2.3 Wait Processing State

The wait processing state is a low power consumption mode entered by execution of the WAIT instruction.

In wait mode, the internal clock is disabled from all internal circuitry except the internal peripherals (the in-

terrupt controller and host interfaces). All internal processing is halted until any unmasked interrupt occurs,

the DSP96002 is reset, or

D

R is asserted. If exit from the wait state was caused by asserting

D

R,

the processor may enter the debug mode (see

Section 10

).

8.2.4 Stop Processing State

The stop processing state is the lowest power consumption mode and is entered by the execution of the

STOP instruction. In the stop mode, the clock oscillator is gated off, in contrast to the wait mode where the

clock oscillator remains active. All activity in the processor is halted until one of the following actions occurs:

1. A low level is applied to the

I

R

Q

A pin (

I

R

Q

A asserted)

2. A low level is applied to the

R

E

S

E

T pin (

R

E

S

E

T asserted)

3. A low level is applied to the

D

R pin.

Either of these actions will gate on the oscillator and, after a clock stabilization delay, clocks to the proces-

sor and peripherals will be re-enabled.

When the clocks to the processor and peripherals are re-enabled then the processor will enter the reset

processing state if the exit from stop state was caused by a low level on the

R

E

S

E

T pin.

If the exit from stop state was caused by a low level on the

I

R

Q

A pin then the processor will service

the highest priority pending interrupt. If no interrupt is pending (i. e.

I

R

Q

A was deasserted before

interrupts were arbitrated) then the processor resumes execution at the instruction following the STOP in-

struction that caused the entry into the stop state.

If the exit from stop state was caused by a low level on the

D

R pin, the processor may enter the debug

mode (see

Section 10

).

8.3

EXCEPTION PROCESSING

Exception processing in a digital signal processing environment is primarily associated with transfer of data

between DSP96002 memory or registers and a peripheral device. When an interrupt occurs, a limited con-

text switch must be performed with minimum overhead.

When a hardware interrupt is received, it is synchronized on instruction boundaries so that the first two in-

terrupt instruction words can be inserted into the instruction stream. Suppose that the interrupt is stored

in the interrupt pending latch during the current instruction fetch cycle. During the next cycle, which is the

decode cycle of the current instruction, the PC will be updated to fetch the next instruction. However, in

the following cycle, which is the execution cycle of the current instruction, the address placed on the pro-

gram address bus (PAB) comes from the appropriate interrupt start address, rather than from the PC. Note

that the PC is frozen until exception processing terminates.

Figure 8-1illustrates the effect of the interrupt controller, which is simply to insert two instruction words into

the processor’s instruction stream.