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Bsclr branch to subroutine if bit clear bsclr – Motorola DSP96002 User Manual

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MOTOROLA

DSP96002 USER’S MANUAL

A - 51

BSCLR

Branch to Subroutine if Bit Clear

BSCLR

Operation:

If S{n} = 0,then PC

SSH; SR

SSL; PC + xxxx

PC

else

PC + 1

PC

If S{n} = 0,then PC

SSH; SR

SSL; PC + xxxx

PC

else

PC + 1

PC

If S{n} = 0,then PC

SSH; SR

SSL; PC + xxxx

PC

else

PC + 1

PC

If S{n} = 0,then PC

SSH; SR

SSL; PC + xxxx

PC

else

PC + 1

PC

If S{n} = 0,then PC

SSH; SR

SSL; PC + xxxx

PC

else

PC + 1

PC

If S{n} = 0,then PC

SSH; SR

SSL; PC + xxxx

PC

else

PC + 1

PC

If S{n} = 0,then PC

SSH; SR

SSL; PC + xxxx

PC

else

PC + 1

PC

Assembler Syntax:

BSCLR #bit,X: ea, label

BSCLR #bit,X: aa, label

BSCLR #bit,X: pp, label

BSCLR #bit,Y: ea, label

BSCLR #bit,Y: aa, label

BSCLR #bit,Y: pp, label

BSCLR #bit,S,label

Description:

The nth bit in the source operand is tested. If the tested bit is cleared, the address of the instruction im-

mediately following the BSCLR instruction and the status register are pushed onto the stack. Program

execution then continues at location PC+displacement. The PC contains the address of the next instruc-

tion. If the tested bit is set, the PC is incremented and program execution continues sequentially. How-

ever, the address register specified in the effective address field is always updated independently of the

condition. The displacement is a 2’s complement 32-bit integer that represents the relative distance from

the current PC to the destination PC. The 32-bit displacement is contained in the extension word of the

instruction. All memory alterable addressing modes may be used to reference the source operand. Ab-

solute Short, I/O Short and Register Direct addressing modes may also be used. Note that if the specified

source operand S is the SSH, the stack pointer register will be decremented by one; if the condition is true,

the push operation will write over the stack level where the SSH value was taken. The bit to be tested is

selected by an immediate bit number 0-31. See Section A.10 for restrictions.

CCR Condition Codes: Not affected.

ER Status Bits: Not affected.

IER Flags: Not affected.