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Motorola DSP96002 User Manual

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DSP96002 USER’S MANUAL

MOTOROLA

4.11.2 The Arbitration Protocol

The bus is arbitrated by a central bus arbitrator, using individual request/grant lines to each bus master.

The arbitration protocol can operate in parallel with bus transfer activity so that the bus hand-over can be

made without much performance penalty.

The arbitration sequence occurs as follows:

5:12. All candidates for bus ownership assert their respective

B

R signals as soon as they need

the bus.

5:13. The arbitration logic designates a bus master-elect by asserting the

B

G signal for that de-

vice.

5:14. The master-elect tests

B

B to ensure that the previous master has relinquished the bus.

If

B

B is deasserted, then the master-elect asserts

B

A, which designates the device as

the new bus master. If a higher priority bus request occurs before the

B

B signal was

deasserted, then the arbitration logic may replace the current master-elect with the higher

priority candidate. However, only one

B

G signal must be asserted at one time.

5:15. The new bus master begins its bus transfers after the assertion of

B

A.

5:16. The arbitration logic signals the current bus master to relinquish the bus by deasserting

B

G at any time. A DSP96002 bus master releases its ownership (deasserts

B

A) after

completing the current external bus access. If an instruction is executing a Read-Modify-

Write external access, a DSP96002 master asserts the

B

L signal and will only relinquish

the bus (and deassert

B

L) after completing the entire Read-Modify-Write sequence.

When the current bus master deasserts

B

A, the

B

B signal must also be deasserted

because the next bus master-elect has received its

B

G signal and is waiting for

B

B to

be deasserted before claiming ownership.

The DSP96002 has 2 control bits and one status bit, located in the Bus Control Registers (see Section 7)

to permit software control of the

B

R and

B

L signals, and to verify when the chip is the bus master.

If the RH bit in the BCR register is cleared, the DSP96002 asserts its

B

R signal only as long as requests

for bus transfers are pending or being attempted. If the RH bit is set,

B

R will remain asserted. If the

LH bit in the BCR register is cleared, the DSP96002 asserts its

B

L signal only during a read-modify-

write bus access. If the LH bit is set,

B

L will remain asserted.

5.16.1 Arbitration Scheme

The bus arbitration scheme is implementation dependent. The diagram in Figure 2-7 illustrates a common

method of implementing the bus arbitration scheme. The arbitration logic determines the device priorities

and assigns bus ownership depending on those priorities.