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Motorola DSP96002 User Manual

Page 830

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MOTOROLA

7.1

DCS Reserved Bits (Bits 6, 7, 17-22, 27, 29)

These bits read as zero and should be written with zero for future compatibility.

7.2

DCS DMA Request Masks (M0-M8) Bits 8-16

The DMA Request mask bits select the source of DMA requests used to trigger DMA
transfers. If a mask bit is set, the corresponding device is selected as the DMA request
source. If the mask bit is cleared, the device is ignored. The DMA request sources may
be the internal peripherals or external devices requesting service through the IRQA,
IRQB and IRQC pins. The external inputs behave as edge-triggered synchronous inputs.
The mask bits are cleared by hardware and software reset. The internal DMA request
sources are produced by ANDing the internal peripheral status bits with DE.


DMA Source Modifier Register

DSM1

addr X:$FFFFFFD7

DMA Source Address Register

DSR1

addr X:$FFFFFFD6

DMA Source Offset Register

DSN1

addr X:$FFFFFFD5

DMA Destination Modifier Register

DDM1

addr X:$FFFFFFD3

DMA Destination Address Register

DDR1

addr X:$FFFFFFD2

DMA Destination Offset Register

DDN1

addr X:$FFFFFFD1

DMA Counter

DCO1

addr X:$FFFFFFD4

31

30

29

28

27

26

25

24

DMA Control/Status Register
DCS1

DE

DIE

*

DTD

*

DTM1 DTM0

DMAP

addr X:$FFFFFFD0

23

22

21

20

19

18

17

16

DCP

*

*

*

*

*

*

M8

15

14

13

12

11

10

9

8

M7

M6

M5

M4

M3

M2

M1

M0

7

6

5

4

3

2

1

0


*

*

DSS2

DSS1 DSS0 DDS2

DDS1

DDS0

Figure 21 - DMA Controller Programming Model - Channel 1

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