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Motorola DSP96002 User Manual

Page 891

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Index (Continued)

INDEX - 4

MOTOROLA

Codec Status Register (COSR)

. 6-6

,

6-9

,

49

Codec Transmit Data Register

. . . . . . 6-6

Comb Filter

. . . . . . . . . . . . . . . . . . . . . 6-3

Command Vector Register

. . . . . . . . . 5-7

Command Vector Register (CVR)

. . . . .55

Companding/Expanding Hardware

. . 8-17

Compare Interrupt Enable (CIE) Bit 10

7-7

Condition Code Register

. . . . . . . . . . 1-21

Conditional Program Controller Instruc-

tions

. . . . . . . . . . . . . . . . . . . . . .38

Control Register (PBC)

. . . . . . . . . . 51

,

53

Control Register (PCC)

. . . . . . . . . . . . .52

COSR Codec Receive Data Full Bit

(CRDF)

. . . . . . . . . . . . . . . . . . 6-10

COSR Codec Receive Overrun Error Flag

Bit (CROE)

. . . . . . . . . . . . . . . 6-10

COSR Codec Transmit Data Empty Bit

(CTDE)

. . . . . . . . . . . . . . . . . . 6-10

COSR Codec Transmit Under Run Error

FLag Bit (CTUE)

. . . . . . . . . . . . 6-9

CRA Frame Rate Divider Control

(DC0…DC4) Bits 8-12

. . . . . . 8-13

CRA Prescale Modulus Select

(PM0…PM7) Bits 0-7

. . . . . . . 8-13

CRA Prescaler Range (PSR) Bit 15

. 8-15

CRA Word Length Control (WL0,WL1) Bits

13, 14

. . . . . . . . . . . . . . . . . . . 8-14

CRB A/Mu Law Selection Bit (A/MU) Bit 3

8-17

CRB Clock Polarity Bit (SCKP) Bit 6

. 8-17

CRB Clock Source Direction (SCKD) Bit 5

. . . . . . . . . . . . . . . . . . . . . . . . 8-17

CRB Frame Sync Invert (FSI) Bit 9

. . 8-17

CRB Frame Sync Length (FSL) Bit 8

8-17

CRB MSB Position Bit (SHFD) Bit 7

. 8-17

CRB Serial Output Flag 0 and 1 (OF0,

OF1) Bit 0, 1

. . . . . . . . . . . . . . 8-16

CRB SSI0 Mode Select (MOD) Bit 11

8-18

CRB SSI0 Receive Enable (RE) Bit 13

. 8-

18

CRB SSI0 Receive Interrupt Enable (RIE)

Bit 15

. . . . . . . . . . . . . . . . . . . 8-19

CRB SSI0 Transmit Enable (TE) Bit 12

8-

18

CRB SSI0 Transmit Interrupt Enable (TIE)

Bit 14

. . . . . . . . . . . . . . . . . . . 8-19

CRB Sync/Async (SYN) Bit 10

. . . . . 8-18

CVR Host Command Bit (HC) Bit 7

. . 5-9

CVR Host Vector

. . . . . . . . . . . . . . . . 5-7

—D—

D/A Analog Comb Decimating Filter

6-21

D/A Analog Comb Filter Transfer Function

. . . . . . . . . . . . . . . . . . . . . . . . 6-21

D/A Analog Low Pass Filter

. . . . . . . 6-24

D/A Comb Filter Transfer Function

. 6-19

D/A Interpolation Filter

6-35

,

6-43

,

6-51

,

6-

59

D/A Second Order Digital Comb Filter

. 6-

19

D/A Section

. . . . . . . . . . . . . . . . . . . . 6-5

D/A Section DC Gain

. . . . . . . . . . . . 6-17

D/A Section Frequency Response and DC

Gain

. . . . . . . . . . . . . . . . . . . . 6-17

D/A Section Overall Frequency Response

6-26

Data ALU Instructions

. . . . . . . . . . . . . 40

Data ALU Instructions with One Parallel

Operation

. . . . . . . . . . . . . . . . . . 33

Data Direction Register (PBDDR)

. . . . 51

Data Direction Register (PCDDR)

. . . . 52

Data Register (PBD)

. . . . . . . . . . . . . . 51

Data Register (PCD)

. . . . . . . . . . . . . . 52

Decimation

. . . . . . . . . . . . . . . . . . . . . 6-3

Decimation/Interpolation

. . . . . . . . . 6-67

Decimation/Interpolation Ratio Control

6-8

Decrement Ratio (DC7-DC0) Bit 0-7

. 7-6

Differential Output

. . . . . . . . . . . . . . . 6-4

Division Instruction

. . . . . . . . . . . . . . . . 39

DMA Mode Operation

. . . . . . . . . . . 5-18

Double Precision Data ALU Instructions

.

39

DSP Programmer Considerations

. . 5-23

DSP Reset

. . . . . . . . . . . . . . . . . . . . . 8-8

DSP to Host

. . . . . . . . . . . . . . . . . . . 5-20