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Ation, and appendix a giv, Appendix a – instruction set addendum details – Motorola DSP96002 User Manual

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MOTOROLA

7.4.1

Reserved bits (Bits 12-15, 28-31)

These reserved bits read as zero and should be written with zero for future compatibility.

7.4.2

Timer 0 Interrupt Priority Level - T0L1-T0L0 (Bits 24-25)

The Timer 0 Interrupt Priority Level (T0L1-T0L0) bits are used to enable and specify the
priority level of the Timer 0 interrupt.

7.4.3

Timer 1 Interrupt Priority Level - T1L1-T1L0 (Bits 26-27)

The Timer 1 Interrupt Priority Level (T1L1-T1L0) bits are used to enable and specify the
priority level of the Timer 1 interrupt.

APPENDIX A – INSTRUCTION SET ADDENDUM DETAILS

The following pages present a detailed description of the new instructions added to the
DSP96002 instruction set.

T0L1 T0L0 Enabled Int. Priority Level (IPL)

0

0

no

-

0

1

yes

0

1

0

yes

1

1

1

yes

2

T1L1 T1L0 Enabled Int. Priority Level (IPL)

0

0

no

-

0

1

yes

0

1

0

yes

1

1

1

yes

2