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Motorola DSP96002 User Manual

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DSP96002 USER’S MANUAL

MOTOROLA

Block transfer mode is selected. Clearing DE during DMA operation will stop the DMA only after the present

DMA transfer has been completed (the data is stored in the destination), setting DTD.

7.5.4 DMA Counter (DCO)

The DMA Counter is a read/write 32-bit register that contains the number of DMA data transfers to be done.

If the DMA channel is set to Single Block transfer mode then, after each DMA data transfer, the DMA

Counter is decremented by one and tested for zero. When the count reaches zero, the DMA Block transfer

is done and the DMA channel will stop the data transfers. If the channel is set to Single Word mode (DTM1-

DTM0=11), the contents of the DMA counter are ignored since each DMA data transfer is done on demand.

The DMA Counter should not be written while the DMA channel is operating in one of the Block Transfer

modes. The DMA Counter may be written only when the channel is disabled (DE=0 and DTD=1), or when

in Single Word mode (DTM1-DTM0=11).

7.5.5 DMA Address Registers (DSR and DDR)

The DMA Source Address register (DSR) and the DMA Destination Address register (DDR) are two 32-bit

registers that contain the addresses of the source and destination, respectively, for the next DMA transfer.

The DMA Address registers are functionally identical to the Address Generation Unit address registers.

7.5.6 DMA Offset Registers (DSN and DDN)

The DMA Source Offset register (DSN) and the DMA Destination Offset register (DDN) are two 32-bit reg-

isters that specify the offset values used to update the respective DMA address registers. Each offset reg-

ister is read when the associated address register is read and used as input to its modulo arithmetic unit.

The DMA Offset registers are functionally identical to the Address Generation Unit offset registers.

7.5.7 DMA Modifier Registers (DSM and DDM)

The DMA Source Modifier register (DSM) and the DMA Destination Modifier register (DDM) are two 32-bit

registers that specify the type of arithmetic used to update the respective DMA address register during DMA

address register update calculations. Each modifier register is read when the associated address register

is read and used as input to its modulo arithmetic unit. The DMA Modifier registers are functionally identical

to the Address Generation Unit modifier registers. Both DMA modifier registers are set to $FFFFFFFF (lin-

ear arithmetic) during a processor reset or software reset.

7.5.8 DMA ALU

The ALU is common to the DMA and Address Generation Unit, and time multiplexed between them. The

DMA ALU is hardwired in the (R)+N configuration. Users can increment or decrement by 1 or N by loading

the DMA Offset registers accordingly. For example, DMA block transfers with DSP96002 word addressable

memory would often load the DMA Offset register with +1. However, interpolation, decimation, and commu-

tation operations could require an arbitrary address offset value N. DMA block transfers with byte address-

DE

DMA Operation

0 Disabled

1 Enabled