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Motorola DSP96002 User Manual

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8 - 10

DSP96002 USER’S MANUAL

MOTOROLA

31 30 29 28 27 26 25 24

** ** ** ** ** ** ** **


Reserved

23 22 21 20 19 18 17 16

HBL1 HBL0 HAL1 HAL0 D1L1 D1L0 D0L1 D0L0


DMA Channel 0 IPL

DMA Channel 1 IPL

Host A IPL

Host B IPL

15 14 13 12 11 10 9 8

** ** ** ** IRCS ICL2 ICL1 ICL0

IRQC IPL
IRQC Trigger Mode
IRQC Status
Reserved

7 6 5 4 3 2 1 0

IRBS IBL2 IBL1 IBL0 IRAS IAL2 IAL1 IAL0

IRQA IPL
IRQA Trigger Mode
IRQA Status
IRQB IPL
IRQB Trigger Mode
IRQB Status

Note: Reserved bits read as zero and should be written with zero
for future compatibility.

Figure 8-9. Interrupt Priority Register IPR (Address X:$FFFFFFFF)

Figure 8-8. Status Register Interrupt Mask Bits

Exceptions

I1 I0 Exceptions Permitted Masked

0 0 IPL 0, 1, 2, 3 None
0 1 IPL 1, 2, 3 IPL 0
1 0 IPL 2, 3 IPL 0,1
1 1 IPL 3 IPL 0,1,2