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Motorola DSP96002 User Manual

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MOTOROLA

DSP96002 USER’S MANUAL

A - 101

FBScc

Floating-Point Branch

FBScc

To Subroutine Conditionally

Description:

If the specified floating-point condition is true, the address of the instruction immediately following the FB-

Scc instruction and the status register are pushed onto the stack. Program execution then continues at a

location specified by a PC relative address in the instruction. If the specified condition is false, the PC is

incremented and the PC relative address is ignored. Short Displacement, Long Displacement, and Ad-

dress Register PC Relative addressing modes may be used. The Short Displacement 15-bit data is sign

extended to form the PC relative displacement. The PC points to the next instruction when it is added to

the displacement. See Section A.10 for restrictions. Non-aware floating-point conditions set the SIOP flag

in the IER and the UNCC bit in the ER if the NAN bit is set. This action occurs before stacking the status

register when the specified non-aware floating-point condition is true.

Assembler Syntax:

FBScc label (short)

FBScc label

FBScc Rn

Operation:

If cc, then PC

SSH; SR

SSL; PC+xx

PC

else PC+1

PC

If cc, then PC

SSH; SR

SSL; PC+xxxx

PC

else PC+1

PC

If cc, then PC

SSH; SR

SSL; PC+Rn

PC

else PC+1

PC