I i___ i i___ i i, F i___ f i___ f i___ f, Toshiba – Toshiba TMP87CP24AF User Manual
Page 85
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TOSHIBA
TMP87CM24A/P24A
External Clock
An external clock connected to the SCK1/SCK2 pin is used as the serial clock. In this case, the
P42 (SCK1)/P45 (SCK2)output latch must be set to " 1 T o ensure shifting, a pulse width of at
least 4 machine cycles is required. Thus, the maximum transfer speed is 244K-bit/s. (at fc =
8
MHz).
SCK pin input
tsCKL tsCKH
tscKL. tscKH > 4 tcyc
Note : tcyc = 4/fc (In NORAML1/2, IDLE1/2 modes)
___________
4/fs (In SLOW, SLEEP modes)
__________
b.Shift edge
The leading edge is used to transmit, and the trailing edge is used to receive.
© Leading Edge
Transmitted
data
are
shifted
on
the
leading
edge
of
the
serial
clock
(falling
edge
of
the
SCK
pin input/output).
@ Trailing Edge
Received data are shifted on the trailing edge of the serial clock (rising edge of the SCK pin
input/output).
SCK pin
SO pin
Shift register
SCK pin
SI pin
Shift register
\
_I I___ I I___ I I
!\ BitO X Bit1 X Bit 2 X Bits
~X 3210 X *321 X **32 X
(a) Leading Edge
f I___ f I___ f I___ f
Y
BitO
X Bit2 X Bits
Y
0*** X~ 10** ^ 210* DC
h
Ì£
*: Don't care
(b) Trailing Edge
Figure 2-36. Shift Edge
(2)
Number of Bits to Transfer
Either
4-bit
or
8
-bit
serial
transfer
can
be
selected.
When
4-bit
serial
transfer
is
selected,
only
the
lower
4
bits
of
the
transmit/receive
data
buffer
register
are
used.
The
upper
4
bits
are
cleared
to
"0"
when receiving.
The data is transferred in sequence starting at the least significant bit (LSB).
3
-
24-85
2002
-
10-03