7 8-bit timer/counter 3 (tc3), 1 configuration, Toshiba – Toshiba TMP87CP24AF User Manual
Page 76
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TOSHIBA
TMP87CM24A/P24A
(3)
Window Mode
In
this
mode,
counting
up
is
performed
on
the
rising
edge
of
the
pulse
that
is
the
logical
AND-ed
product
of
the
TC2
pin
input
(window
pulse)
and
an
internal
clock.
The
internal
clock
is
selected
with
TC2CK.
The
contents
of
TREG2
are
compared
with
the
contents
of
up-counter.
If
a
match
is
found,
an
INTTC2
interrupt
is
generated,
and
the
up-counter
is
cleared
to
"0".
It
is
necessary
that
the
maximum
applied
frequency
(TC2
input)
be
such
that
the
counter
value
can
be
analyzed
by
the
program.
That
is,
the
frequency
must
be
considerably
slower
than
the
selected
internal
clock.
Example :
Inputs "H" level pulse of 120 ms or more and generates interrupt. (atfc =
8
MHz).
LD
(TC2CR), 00000101B
; Sets TC2 mode and source clock.
LDW
(TREG2), 0078H
; SetsTREG2(120ms^2i3/fc = 0078H)
SET
El
LD
(EIRH).EF14
; Enables INTTC2 interrupt
(TC2CR),00100101B
; Starts TC2
TC2 pin input
Internal clock
Up-counter
TREG2
INTTC2 interrupt
n-2
( n <
Match
Counter clear
Figure 2-25. Window Mode Timing Chart
2.7
8-Bit Timer/Counter 3 (TC3)
2.7.1 Configuration
Figure 2-26. Timer/Counter 3
3
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24-76
2002
-
10-03