2 software interrupt (intsw), 3 external interrupts, Toshiba – Toshiba TMP87CP24AF User Manual
Page 37
Attention! The text in this document has been recognized automatically. To view the original document, you can use the "Original mode".
TOSHIBA
TMP87CM24A/P24A
1.9.2 Software Interrupt (INTSW)
Executing
the
[SWI]
instruction
generates
a
software
interrupt
and
immediately
starts
interrupt
processing
(INTSW
is
highest
prioritized
interrupt).
However,
if
processing
of
a
non-maskable
interrupt
is
already
underway,
executing
the
SWI
instruction
will
not
generate
a
software
interrupt
but
will
result
in
the
same
operation
as
the
[NOP]
instruction.
Thus,
the
[SWI]
instruction
behaves
like
the
[NOP]
instruction.
Note: Software interrupt generates during non-maskable interrupt processing to use SWI instruction
for software break in a development tool.
Use the [SWI] instruction only for detection of the address error or for debugging.
©
Address Error Detection
FF
h
is read if for some cause such as noise the CPU attempts to fetch an instruction from a
non-existent
memory
address.
Code
FF
h
is
the
SWI
instruction,
so
a
software
interrupt
is
generated
and
an
address
error
is
detected.
The
address
error
detection
range
can
be
further
expanded
by
writing
FF
h
to
unused
areas
of
the
program
memory.
Address
trap
reset is generated for instruction fetch from a part of RAM area (address
0040
h
to
083F
h
)
or
SFR area (OOOO
h
to
003F
h
).
Note: The fetch data from addresses 3F80
h
to 3FFF
h
(test ROM area) for
TMP87CM24A/P24A is not "FF
h
".
® Debugging
Debugging
efficiency
can
be
increased
by
placing
the
SWI
instruction
at
the
software
break
point setting address.
1.9.3 External Interrupts
The
TMP87CM24A/P24A
have
five
external
interrupts
(INTO
to
INT5
:
INTO,
INTI,
INT2,
INT3,
INT5).
Three
of
these
(INTI,
INT2,
INT3)
have
digital
noise
cancellation
circuits
(pulse
inputs
of
less
than
a
fixed
time
are cancelled as noise). Edge selection is possible with pins INTI, INT2,and INT3.
The INT0/P10 pin can be selected either as an external interrupt input pin or as an I/O port. At reset, it is
initialized as an input port.
Edge
selection,
noise
cancellation
control,
and
INT0/P10
pin
function
selection
are
performed
by
the
external interrupt control register 1 (EINTCR).
The
both-edge
detect
function
of
the
INT3
pin
is
selected
by
the
external
interrupt
control
register
1
(EINTCR) and the external interrupt control register 2 (EINT3CR).
Table
1-3
lists
enable
conditions,
edge
select,
noise
cancellation
conditions.
The
following
are
notes
on
the usage of external interrupts:
3
-
24-37
2002
-
10-03