3 function, Toshiba – Toshiba TMP87CP24AF User Manual
Page 75
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TOSHIBA
TMP87CM24A/P24A
2.6.3 Function
The
timer/counter
2
has
three
operating
modes:
timer,
event
counter
and
window
modes.
Also
timer/counter 2 is used for warm-up when switching from SLOW mode to NORMAL2 mode.
(1)
Timer Mode
In
this
mode,
the
internal
clock
is
used
for
counting
up.
The
contents
of
TREG2
are
compared
with
the
contents
of
up-counter.
If
a
match
is
found,
a
timer/
counter
2
interrupt
(INTTC2)
is
generated,
and the counter is cleared. Counting up is resumed after the counter is cleared.
Also,
when
fc
is
selected
as
the
source
clock
during
SLOW
mode,
the
lower
11
bits
of
TREG2
are
ignored
and
an
INTTC2
interrupt
is
generated
by
matching
the
upper
5
bits.
Thus,
in
this
case,
only
the TREG2
h
setting is necessary.
Table 2-4. Source Clock (Internal Clock) for Timer/Counter 2
Source clock
Resolution
Maximum time setting
NORMAL1/2, DLE1/2mode
SLOW mode
SLEEP mode
DV7CK = 0
DV7CK= 1
Atfc = 8MHz At fs = 32.768 kHz
Atfc = 8MHz
At fs = 32.768 kHz
fc/2^3[Hz]
fs/2’=[Hz]
fs/2’= [Hz]
fs/2’= [Hz]
1.05 [s]
1 [s]
19.1
[h]
18.2 [h]
fc/2’^
fs/2=
fs/2=
fs/2=
1.02 [ms]
1 [ms]
1.1
[m]
1 [m]
fc/2»
fc/2»
-
-
32 [/.s]
-
2.1
[s]
-
fc/2^
fc/2^
-
-
1 [
a
*
s
]
-
65.5
[ms]
-
-
-
fc (Note)
-
125 [ns]
-
7.936 [ms]
-
fs
fs
-
-
-
30.5
[jus]
-
2 [s]
Note : "fc" can be used only in the timer mode. This is used for warm up when switching from SLOW
mode to NORMAL2 mode.
Example : Sets the timer mode with source clock
fc/23
[Hz] and generates an interrupt every 25ms
(at fc =
8
MHz).
Sets the TC2 mode and source clock
SetsTREG2(25ms^23/fc =
61A8
h
)
Enable INTTC2
; Starts TC2
LD
(TC2CR), 000011008
LDW
(TREG2),61A8H
SET
(EIRH).EF14
El
LD
(TC2CR), 001011008
(2)
Event Counter Mode
In this mode, events are counted on the rising edge of the
TC2
pin input. The contents of
TREG2
are
compared
with
the
contents
of
the
up-counter.
If
a
match
is
found,
an
INTTC2
interrupt
is
generated,
and
the
counter
is
cleared.
The
maximum
frequency
applied
to
the
TC2
pin
isfc/24
[Hz]
in
NORMAL1/2
or
IDLE1/2
mode, and
fs/24
[Hz] in
SLOW
or
SLEEP
mode. But, a pulse width of
2
machine
cycles or more is required for both "H" and "L" level.
Example : Sets the event counter mode and generates an INTT2 interrupt 640 counts later.
LD
(TC2CR), 000111008
; Sets the TC2 mode
LDW
(TREG2), 640
; SetsTREG2
SET
El
LD
(EIRH).EF14
; Enable INTTC2
(TC2CR),001111008
; Starts TC2
3
-
24-75
2002
-
10-03