2 control, Toshiba – Toshiba TMP87CP24AF User Manual
Page 66
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TOSHIBA
TMP87CM24A/P24A
2.5.2 Control
The
timer/counter
1
is
controlled
by
a
timer/counter
1
control
register
(TC1CR)
and
two
16-bit
timer
registers (TREG1A and TREG1B). Reset does not affect TREG1A and TREG1B.
TREG1A
(0010, 001 1
h
)
TREG1B
(0012,0013
h
)
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
TREGIAu (0011
h
)
_____ 1____ 1____ 1____
x
L
j
___ iHi___ 1____ 1____
, , TREG1A
l
(0010,
h
)
Write only
, , TREG1B^^(0013н)
, , TREG 18^(0012^)
7
6
5 4
3 2
1 0
TC1CR
(0014
h
)
TFF1
SCAPI
MCAP1
METTI
MPPG1
TC1S
_____ 1____
TC1CK
_____ 1____
TC1M
_____ 1____
Read/Write (Write available in only PPG
output mode)
(Initial value : 0000 0000)
00
Timer/external trigger timer/event counter mode
TC1M
TCI
01
Window mode
mode select
10
Pulse width measurement mode
11
PPG output mode
00
Internal clock fc/2" or fs/2^ [Hz]
TC1CK
TCI
01
Internal clock fc/2^
source clock select
10
Internal clock fc/2^
11
External clock (TCI pin nput)
00
Stop and counter clear
TC1S
TCI
01
Command start
start control
10
Reserved
11
External trigger srart
SCAPI
Software capture control
0
1 : Software capture trigger (Note 3)
MCAP1
Pulse width measurement
control
1
: Double edge capture 1 : Single edge capture
METTI
External trigger timer
control
0
: Trigger srart 1 : Trigger start and stop
MPPG1
PPG output control
0
: Cotinuous pulse 1 : Single pulse
TFF1
Timer F/F1 control for PPG
output mode
0
: Clear 1 : Set
Write
only
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz]
Writing
to
the
low-byte
of
the
timer
registers
(TREGIA
l
,
TREGIBi),
the
comparison
is
inhibited
until
the
high-byte
(TREGIA
h
,
TREGIB
h
)
is
written.
(Only
the
low-byte
of
the
timer
registers
cannot
be
changed.)
After
writing
to
the
high-byte,
the
comparison
within
1
cycle
(during
instruction execution) is ignored.
Set the mode, source clock, edge (INT2ES), PPG control and timer F/F1 control when TCI stops
(TCI S = 00).
Software
capture
can
be
used
in
only
timer
and
event
counter
modes.
SCAP1
is
automatically
cleared to "0" after software capture.
Values to be loaded to timer registers must satisfy the following condition.
TREG1A>TREG1B>0 (PPG output mode) ; TREG1A>0 (others)
Always write "0" to TFF1 except the PPG output mode.
TC1CR is a write-only register, which cannot access any of in read-modify-write instruction such
as bit operate, etc.
TREG1B cannot be written after setting to PPG output mode.
In case of fc/23 is selected on the pulse width measurement mode. The LSB of counter (TREG1B)
is always "0". In the other source clock is selected, the value of counter correspond with real
count.
Figure 2-15. Timer Registers and TCI Control Register
3
-
24-66
2002
-
10-03