Toshiba TMP87CP24AF - Manual (Page 50)

TOSHIBA
TMP87CM24A/P24A
1.10.4 Watchdog Timer Reset
If the watchdog timer output becomes active, a reset is generated, which drives the RESET pin low to
reset the internal hardware. The reset output time is 220/fc [s] (131 ms at fc = 8 MHz). The RESET pin is
sink open drain input/output with pull-up resistor.
Note: The high-frequency clock oscillator also turns on when a watchdog timer reset is generated in
SLOW mode. Thus, the reset output time is 220ifc.
The reset output time include a certain amount of error if there is any fluctuation of the
oscillation frequency when the high-frequency clock oscillator turns on. Thus, the reset output
time must be considered approximate value.
2’7fc [s]
Clock
Binary counter
Overflow
INTWDT interrupt
WDT reset output
”L
; ^ 2’7fc ^ :
i_____ ____ ^____ <____ i_____ )^ __________ ;
J~T w DTT = 11
b )
writes 4E h to WDTCR2
(High-Z) ~|("L" output)
Figure 1-29. Watchdog Timer Interrupt/Reset
1.11 Reset Circuit
The TMP87CM24A/P24A each have four types of reset generation procedures: an external reset input, an
address trap reset, a watchdog timer reset and a system clock reset. Table 1-5 shows on-chip hardware
initialization by reset action. The internal source reset circuit (watchdog timer reset, address trap reset,
and system clock reset) is not initialized when power is turned on. Thus, output from the RESET pin may
go low (220/fc [s] (131 ms at 8 MHz) when power is turned on.
Table 1-5. Initializing Internal Status by Reset Action
On-chip Hardware Initial Value
Divider of Timing generator 0
Watchdog timer Enable
Output latches of I/O ports
Refer to I/O port
circuitry
Control registers
Refer to each of
control register
On-chip Hardware Initial Value
Program counter (PC)
Register bank selector (RBS)
Jump status flag (JF)
Interrupt master enable flag (IMF)
Interrupt individual enable flags (EF)
Interrupt latches (IL)
(FFFF h )-(FFFE h )
0
1
0
0
0
3
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24-50 2002
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10-03