I)gz)gz)c2:xiz)gzn^xhxzdgz), Toshiba – Toshiba TMP87CP24AF User Manual
Page 68
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TOSHIBA
TMP87CM24A/P24A
Command start
Source clock
Up-counter
TREG1A
INTTC1 interrupt
Source clock
Up-counter
JlAllJlJlJinvrLnnnn^^
0
;
X
Match
Counter
detect \rr
(a) Timer
I)GZ)GZ)C2:XiZ)GZn^XHXZDGZ)(
TREG1B
SCAPI
X
Capture
n
Capture
11
n
(b) Software Capture
Figure 2-16. Timer Mode Timing Chart
(2)
External Trigger Timer mode
In
this
mode,
counting
up
is
started
by
an
external
trigger.
This
trigger
is
the
edge
of
the
TCI
pin
input. Either the rising or falling edge can be selected. Edge selection is the same as for the external
interrupt
input
INT2
pin.
Source
clock
is
used
an
internal
clock
selected.
The
contents
of
TREG1A
is
compared
with
the
contents
of
up-counter.
If
a
match
is
found,
an
INTTC1
interrupt
is
generated,
and the counter is cleared to"0" and halted.
The counter is restarted by the selected
edge of the TCI
pin input.
When the edge input is opposite to the edge input way of the count start trigger at METTI (bit
6
in
TC1CR)
=
1,
the
counter
is
cleared,
and
count
stops.
In
this
mode,
pulse
input
with
a
constant
pulse
width
generates
interrupt.
When
METTI
is
"0",
the
opposite
edge
input
is
ignored.
The
edge
of
TCI
pin input before match detection is also ignored.
The TCI pin input has the same noise rejection as the INT2 pin; therefore, pulses of 7/fc [s] or less are
rejected
as
noise.
A
pulse
width
of
24/fc
[s]
or
more
is
required
for
edge
detection
in
NORMAL1/2
or
IDLE1/2 mode. The noise rejection circuit is turned off in SLOW and SLEEP modes. But, a pulse width
of 4/fs [s] or more is required.
Example 1 :Generates interrupt after 100 /¿sfrom TCI pin input rising edge (at fc =
8
MHz).
LD
(EINTCR),00000000B
INT2ES<-0 (rising edge)
LDW
(TREG1A),0064H
100 //s ^ 23/fc
=
64
h
SET
El
LD
(EIRL).EF4
Enables INTTC1 interrupt
(TC1CR), 00111000B
Starts TCI external trigger, METT = 0
> 2
:When
(at fc =
"L" level pulses of 4ms or more is input to TCI pin, generates interrupt
8
MHz)
LD
(EINTCR), 000001OOB
INT2ES<-1 ("L" level)
LDW
(TREG1A), OOFAH
4 ms T 27/fc
=
FA
h
SET
El
LD
(EIRL).EF4
Enables INTTC1 interrupt
(TC1CR), 011101 OOB
Starts TCI external trigger, METT
=
1
3
-
24-68
2002
-
10-03