1 clock generator, 2 timing generator, Toshiba – Toshiba TMP87CP24AF User Manual
Page 16
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TOSHIBA
TMP87CM24A/P24A
1.8.1 Clock Generator
The
clock
generator
generates
the
basic
clock
which
provides
the
system
clocks
supplied
to
the
CPU
core
and
peripheral
hardware.
It
contains
two
oscillation
circuits:
one
for
the
high-frequency
clock
and
one
for
the
low-frequency
clock.
Power
consumption
can
be
reduced
by
switching
of
the
system
clock
controller to low-power operation based on the low-frequency clock.
The
high-frequency
(fc)
and
low-frequency
(fs)
clocks
can
be
easily
obtained
by
connecting
a
resonator
between
the
XIN/XOUT
and
XTIN/XTOUT
pins,
respectively.
Clock
input
from
an
external
oscillator
is
also
possible.
In
this
case,
external
clock
is
applied
to
the
XIN/XTIN
pin
with
the
XOUT/XTOUT
pin
not
connected. The TMP87CM24A/P24A are not provided an RC oscillation.
High-frequency clock
XIN
□
XOUT
□
Of
(a) Crystal/Ceramic
resonator
XIN
XOUT
□
(open)
(b) External oscillator
Low-frequency clock
XTIN
□
XTOUT
□
XTIN
Of
(c) Crystal
XTOUT
□
(open)
(d) External oscillator
Figure 1-10. Examples of Resonator Connection
A/oie;
Accurate Adjustment of the Oscillation Frequency:
Although no hardware to externally and directly monitor the basic clock pulse is not provided,
the
oscillation
frequency
can
be
adjusted
by
making
the
program
to
output
fixed
frequency
pulses
to
the
port
while
disabling
all
interrupts
and
monitoring
this
pulse.
With
a
system
requiring
adjustment
of
the
oscillation
frequency,
the
adjusting
program
must
be
created
beforehand.
1.8.2 Timing Generator
The
timing
generator
generates
from
the
basic
clock
the
various
system
clocks
supplied
to
the
CPU
core
and peripheral hardware. The timing generator provides the following functions :
© Generation of main system clock
©
Generation of divider output (DVO) pulses
Generation of source clocks for time base timer
Generation of source clocks for watchdog timer
Generation of internal source clocks for timer/counters TCI -TC3, TC5
Generation of internal clocks for serial interfaces SI01 and SI02
Generation of warm-up clocks for releasing STOP mode
Generation of a clock for releasing reset output
(1)
Configuration of Timing Generator
The
timing
generator
consists
of
a
21-stage
divider
with
a
divided-by-4
prescaler,
a
main
system
clock
generator,
and
machine
cycle
counters.
An
input
clock
to
the
7th
stage
of
the
divider
depends
on
the operating mode and DV7CK (bit 4 in TBTCR) shown in Figure 1-11 as follows.
During
reset
and
at
releasing
STOP
mode,
the
divider
is
cleared
to
"0",
however,
the
prescaler
is
not
cleared.
3
-
24-16
2002
-
10-03