Toshiba TMP87CP24AF - Manual (Page 47)

TOSHIBA
TMP87CM24A/P24A
1.10 Watchdog Timer (WDT)
The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the
like, and resumes the CPU to the normal state.
The watchdog timer signal for detecting malfunction can be selected either a reset output or a non­
maskable interrupt request. However, selection is possible only once after reset. At first the reset output
is selected.
When the watchdog timer is not being used for malfunction detection, it can be used as a timer to
generate an interrupt at fixed intervals.
Note: Care must be given in system design so as to protect the Watchdog Timer from disturbing noise.
Otherwise the Watchdog Timer may not fully exhibit its functionality.
1.10.1 Watchdog Timer Configuration
MPX Reset release signal from T.G.
I RESET
INTWDT
Figure 1-27. Watchdog Timer Configuration
1.10.2 Watchdog Timer Control
Figure 1-28 shows the watchdog timer control registers (WDTCR1, WDTCR2). The watchdog timer is
automatically enabled after reset.
(1) Malfunction detection methods using the watchdog timer
The CPU malfunction is detected as follows.
© Setting the detection time, selecting output, and clearing the binary counter.
@ Repeatedly clearing the binary counter within the setting detection time.
If the CPU malfunction occurs for any cause, the watchdog timer output will become active at the
rising of an overflow from the binary counters unless the binary counters are cleared. At this time,
when WDTOUT = 1 a reset is generated, which drives the RESET pin low to reset the internal
hardware and the external circuits. When WDTOUT = 0, a watchdog timer interrupt (INTWDT) is
generated.
The watchdog timertemporarily stops counting in the STOP mode including warm-up or IDLE mode,
and automatically restarts (continues counting) when the STOP/IDLE mode is released.
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