Toshiba TMP87CP24AF - Manual (Page 21)

TOSHIBA
TMP87CM24A/P24A
System Control Register 1
7 6 5
SYSCR1
(0038 h )
STOP RELM RETM OUTEN WUT
_______ 1______
(Initial value: 0000 00**)
STOP
RELM
RETM
OUTEN
WUT
STOP mode start
Release method
for STOP mode
Operating mode
after STOP mode
Port output control
during STOP mode
Warming-uptime at
releasing STOP mode
0 : CPU core and peripherals remain active
1 : CPU core and peripherals are halted
(start STOP mode)
00
01
1 *
Edge-sensitive release
Level-sensitive release
Return to NORMAL mode
Return to SLOW mode
High-impedance
Remain unchanged
3 X 2’7fc or 3 X 2’Vfs
2’7fc or 2 ’Vfs
Reserved
[s]
R/W
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Always set RETM to "0" when transiting from NORMAL1 mode to STOP1 mode and from NOMAL2
mode to STOP2 mode. Always set RETM to "1" when transiting from SLOW mode to STOP2 mode.
When STOP mode is released with RESET pin input, a return is made to NORMAL mode regardless
of the RETM contents.
fc: High-frequencyclocklHz]
fs: Low-frequency clock [Hz]
*; Don't care
Bits 1 and 0 in SYSCR1 are read in as undefined data when a read instruction is executed.
When the STOP mode is started by specifying OUTEN = "0", the internal input of port is fixed to
"0" and the interrupt of the falling edge may be set.
System Control Register 2
7 6 5 4
SYSCR2
(0039 h ) SYSCK IDLE
(Initial value: 10/100 **** )
XEN
High-frequency oscillator 0 : Turn off oscillation
control 1 : Turn on oscillation
XTEN
Low-frequency oscillator 0 : Turn off oscillation
control 1 : Turn on oscillation
SYSCK
Main system clock select
(write)/main
system clock
monitor (read)
0 : High-frequency clock
1 : Low-frequency clock
IDLE IDLE mode start
0 : CPU and watchdog timer remain active
1 : CPU and watchdog timer are stopped (start IDLE mode)
R/W
Note 1
Note 2
Note3
Note 4
Note 5
Note 6:
A reset is applied (RESET pin output goes low) if both XEN and XTEN are cleared to "0".
Do not clear XEN to "0" when SYSCK = 0, and do not clear XTEN to "0" when SYSCK = 1.
WDT: watchdog timer, * : Don't care
Bits 3to0 in SYSCR2 are always read in as "1" when a read instruction is executed.
An optional initial value can be selected for XTEN. Always specify when ordering ES (engineering
sample).
XTEN operating mode after reset
0 Single-clock mode (NORMAL1)
1 Dual-clock mode (NORMAL2)
The instruction for specifying Masking Option (Operating Mode) in ES Order Sheet is described in
ADDITIONAL INFORMATION "Notice for Masking Option of TLCS-870 series" section 8.
Figure 1-15. System Control Registers
3
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24-21 2002
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10-03