Toshiba, 003a, 003b – Toshiba TMP87CP24AF User Manual
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TOSHIBA
TMP87CM24A/P24A
Example 2 : Reads interrupt latches
LD
WA, (IL)
Examples: Tests an interrupt latch
TEST
(IL).7
JR
F,SSET
; W<-IL
h
, A<-IL|_
; ifIl
7
=
1
thenjump
(2)
Interrupt Enable Register
(EIR)
The
interrupt
enable
registers
(EIR)
enable
and
disable
the
acceptance
of
interrupts
except
for
the
pseudo
non-maskable
interrupts
(software
and
watchdog
timer
interrupts).
Pseudo
non-maskable
interrupts
are
accepted
regardless
of
the
contents
of
the
EIR;
however,
the
pseudo
non-maskable
interrupts cannot be nested more than once at the same time.
The
EIR
consists
of
an
interrupt
master
enable
flag
(IMF)
and
individual
interrupt
enable
flags
(EF).
These registers are assigned to addresses
003A
h
and
003B
h
in the SFR, and can be read and written
by an instruction (including read-modify-write instructions such as bit manipulation instructions).
© Interrupt Master enable Flag
(IMF)
The
interrupt
master
enable
flag
(IMF)
enables
and
disables
the
acceptance
of
all
interrupts,
except
for
pseudo
non-maskable
interrupts.
Clearing
this
flag
to
"0"
disables
the
acceptance
of
all
maskable
interrupts.
Setting
to
"
1
"
enables
the
acceptance
of
interrupts.
When
an
interrupt
is
accepted,
this
flag
is
cleared
to
"0"
to
temporarily
disable
the
acceptance
of
maskable
interrupts.
After
execution
of
the
interrupt
service
program,
this
flag
is
set
to
"1"
by
the
maskable
interrupt
return
instruction
[RETI]
to
again
enable
the
acceptance
of
interrupts.
If
an
interrupt
request
has
already
been
occurred,
interrupt
service starts immediately after execution of the [RETI] instruction.
Pseudo
non-maskable
interrupts
are
returned
by
the
[RETN]
instruction.
In
this
case,
the
IMF
is
set
to
"
1
"
only
when
pseudo
non-maskable
interrupt
service
is
started
with
interrupt
acceptance
enabled
(IMF
=
1).
Note
that
IMF
remains
"0"
when
cleared
in
the
interrupt
service program.
The IMF is assigned to bit
0
at address
003A
h
in the SFR, and can be read and written by an
instruction.
IMF
is
normally
set
and
cleared
by
the
[El]
and
[Dl]
instructions,
and
the
IMF
is
initialized to "
0
" during reset.
@ Individual interrupt Enable Flags
(EFisto EF
4
)
These
flags
enable
and
disable
the
acceptance
of
individual
maskable
interrupts,
except
for
an
external
interrupt
0.
Setting
the
corresponding
bit
of
an
individual
interrupt
enable
flag
to "
1
" enables acceptance of an interrupt, setting the bit to "
0
" disables acceptance.
Example 1 : Sets EF for individual interrupt enable, and sets IMF to "1".
(EIR), 1110100010100000B
Dl
LDW
El
Example 2 : Sets an individual interrupt enable flag to
Dl
SET
(EIRH).4
El
IMF
<-0
E F i s t o E F 1 3 , E F 1 1 ,
IMF<-1
IMF
<-0
EF
i
2^1
IMF<-1
EF
7
, EFc
3
-
24-32
2002
-
10-03