Toshiba – Toshiba TMP87CP24AF User Manual
Page 17
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TOSHIBA
TMP87CM24A/P24A
© In the single-clock mode
A divided-by-256 of high-frequency clock
(fc/28)
is input to the 7th stage of the divider.
Do not set DVCKto "1" in the single-clock mode.
@ In the dual-clock mode
During NORMAL2 or IDLE2 mode (SYSCK = 0), an input clock to the 7th stage of the divider
can be selected either
"fc/28"
or "fs" with DV7CK.
During SLOW or SLEEP mode (SYSCK = 1), fs is automatically input to the 7th stage. To input
clock to the 1st stage is stopped ; output from the 1st to 6th stages is also stopped.
MPX: Multiplexer
Figure 1-11. Configuration of Timing Generator
TBTCR
(0036
h
)
(DVOEN)
(DVOCK)
________ 1________
DV7CK
(TBTEN)
(TBTCK)
_________1________ 1________
(Initial value: 0**0 0***)
DV7CK
Selection of input clock to
the 7th staqe of the divider
0 : fc/28 [Hz]
1 : fs
R/W
Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], * : Don't care
Note 2: Do not set DV7CK to "1" in the single-clock mode.
Note 3: Do not set DV7CK to "1" before low-frequency clock is stable in the dual-clock mode.
Figure 1-12. Timing Generator Control Register
(2) Machine Cycle
Instruction
execution
and
peripheral
hardware
operation
are
synchronized
with
the
main
system
clock.
The
minimum
instruction
execution
unit
is
called
an
"machine
cycle".
There
are
a
total
of
10
different
types
of
instructions
for
the
TLCS-870
Series:
ranging
from
1-cycle
instructions
which
require
one
machine
cycle
for
execution
to
10-cycle
instructions
which
require
10
machine
cycles
for
execution.
A machine cycle consists of 4 states (SO - S3), and each state consists of one main system clock.
3
-
24-17
2002
-
10-03