Toshiba – Toshiba TMP87CP24AF User Manual
Page 25
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TOSHIBA
TMP87CM24A/P24A
Note: When STOP mode is released with alow hold voltage, the following cautions must be observed.
The power supply voltage must be at the operating voltage level before releasing STOP mode.
The RESET pin input must also be high, rising together with the power supply voltage. In this
case, if an external time constant circuit has been connected, the RESET pin input voltage will
increase at a slower rate than the power supply voltage. At this time, there is a danger that a
reset may occur if input voltage level of the RESET pin drops below the non-inverting high-
level input voltage (hysteresis input).
(2)
IDLE
mode (IDLE1,IDLE2, SLEEP)
IDLE
mode
is
controlled
by
the
system
control
register
2
and
maskable
interrupts.
The
following
status
is
maintained during IDLE mode.
©
Operation
of
the
CPU
and
watchdog
timer
is
halted.
On-chip
peripherals
continue
to
operate.
@
The
data
memory,
CPU
registers
and
port
output
latches
are
all
held
in
the
status
in
effect before IDLE mode was entered.
(3)
The
program
counter
holds
the
address
of
the
instruction
following
the
instruction
which started IDLE mode.
Example : Starting IDLE mode.
SET
(SYSCR2). 4
IDLE<-1
IDLE
mode
includes
a
normal
release
mode
and
an
interrupt
release
mode.
Selection
is
made
with
the
interrupt
master
enable
flag
(IMF).
Releasing
the
IDLE
mode
returns
from
IDLE1
to
NORMAL1,
from
IDLE2
to
NORMAL2, and from SLEEP to SLOW mode.
a. Normal release mode (IMF = "0")
IDLE
mode
is
released
by
any
interrupt
source
enabled
by
the
individual
interrupt
enable
flag
(EF) or an external interrupt 0 (INTO pin) request.
Execution
resumes
with
the
instruction
following
the
IDLE
mode
start
instruction
(e.g.
[SET
(SYSCR2).4]).
The
interrupt
latch
(IL)
of
the
interrupt
source
for
releasing
the
IDLE
mode
must
be
cleared
to
"
0
" by load instruction.
b. Interrupt release mode (IMF = "1")
IDLE
mode
is
released
and
interrupt
processing
is
started
by
any
interrupt
source
enabled
with
the
individual
interrupt
enable
flag
(EF)
or
an
external
interrupt
0
(INTO
pin)
request.
After
the
interrupt
is
processed,
the
execution
resumes
from
the
instruction
following
the
instruction
which started IDLE mode.
Figure 1-19. IDLE Mode
IDLE
mode
can
also
be
released
by
setting
the
RESET
pin
low,
which
immediately
performs
the
reset
operation.
After
reset,
the
TMP87CM24A/P24A
are
placed
in
NORMAL2
mode
(the
TMP87PP24
is
placed in NORMAL1 mode).
Note: When a watchdog timer interrupt is generated immediately before the IDLE mode is
started, the watchdog timer interrupt will be processed but IDLE mode will not be started.
3
-
24-25
2002
-
10-03