1 interrupt sequence, Dogxhoc, Toshiba – Toshiba TMP87CP24AF User Manual
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TOSHIBA
TMP87CM24A/P24A
1.9.1 Interrupt Sequence
An
interrupt
request
is
held
until
the
interrupt
is
accepted
or
the
interrupt
latch
is
cleared
to
"0"
by
a
reset
or
an
instruction.
Interrupt
acceptance
sequence
requires
8
machine
cycles
(4
jus
at
fc
=
8
MHz
in
NORMAL
mode)
after
the
completion
of
the
current
instruction
execution.
The
interrupt
service
task
terminates
upon
execution
of
an
interrupt
return
instruction
[RETI]
(for
maskable
interrupts)
or
[RETN]
(for pseudo non-maskable interrupts).
(1)
Interrupt acceptance processing
©
The
interrupt
master
enable
flag
(IMF)
is
cleared
to
"0"
to
temporarily
disable
the
acceptance
of
any
following
maskable
interrupts.
When
a
non-maskable
interrupt
is
accepted, the acceptance of any following interrupts is temporarily disabled.
@ The interrupt latch (IL) for the interrupt source accepted is cleared to "0".
(3)
The
contents
of
the
program
counter
(PC)
and
the
program
status
word
are
saved
(pushed)
onto the stack. (Pushed down in order of PSW, PC
h
, PC
l
). The contents of stack pointer (SP)
is decreased by 3.
@
The
entry
address
of
the
interrupt
service
program
is
read
from
the
vector
table
address
corresponding
to
the
interrupt
source,
and
the
entry
address
is
loaded
to
the
program
counter.
d) The instruction stored at the entry address of the interrupt service program is executed.
1-machine cycle
Interrupt service task
Interrupt
I
n
signal
I /1 I
Ir-
Interrupt
latch
!
I I I I I I I I I I I I I I I I I I I I I
Note 2
Instruction
execution
"Z)C
Interrupt acceptance
Instruction \X\
A execution
Ajj A
f
RETI instruction execution
yzz
DOGXHOC
b+lXb + 2Xb + 3,
)OOC
)OEK
Note 1:
a: return address, b: entry address, c: address when the RETI instruction is stored
Note 2:
The maximum response time from when an IL is set until an interrupt acceptance processing starts is
38/fc to 38/fs[s]. It equals to setting the IL on the first machine cycle in 10 cycles instruction execution.
Figure 1-24. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction
Example : Correspondence between vector table address for INTTBT and the entry address of the
interrupt service program.
Vector table address
Entry address
FFF2
h
FFF3
h
03
l
D2,
D203
h
D204
h
OFo
06
h
A
maskable
interrupt
is
not
accepted
until
the
IMF
is
set
to
"1"
even
if
a
maskable
interrupt
of
higher
priority than that of the current interrupt being serviced.
When
nested
interrupt
service
is
necessary,
the
IMF
is
set
to
"1"
in
the
interrupt
service
program.
In
this
case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
3
-
24-34
2002
-
10-03