Toshiba TMP87CP24AF - Manual (Page 8)

TOSHIBA
TMP87CM24A/P24A
Example 1 : Loads the ROM contents at the address specified by the HL register pair
contents into the accumulator (TMP87CM24A : HL^SOOO h ):
LD A, (HL) ; A<-ROM (HL)
Example 2
TABLE :
SNEXT
Converts BCD to 7-segment code (common anode LED). When A = 05 h , 92 h is
output to port P6 after executing the following program:
ADD A, TABLE-$-4 ; P6<-ROM (TABLE + A)
LD (P6), (PC + A)
JRS T, SNEXT ; JumptoSNEXT ^f 9 f b
DB OCOH, 0F9H, 0A4H, OBOH, 99H, 92H, 82H, 0D8H, 80H, 98H
Notes: "$ " is a header address of ADD instruction.
DB is a byte data difinition instruction.
Example 3 N-way multiple jump in accordance with the contents of
accumulator (0^ A^ 3):
SHLC
JP
DW
A ; if A = 00 h then PC<-C234 h
(PC + A) if A = 01H then PC<-C378 h
if A = 02 h then PC<-DA37 h
if A = 03 h then PC<-E1B0 h
0C234H, 0C378H, 0DA37H, 0E1B0H
I Note : DW is a word data definition instruction. Word=2bytes
- JP (PC + A) -
SHLC A
34
C2
78
C3
37
DA
BO
El
1.3 Program Counter (PC)
The program counter (PC) is a 16-bit register which indicates the program memory address where the
instruction to be executed next is stored. After reset, the user defined reset vector stored in the vector
table (addresses FFFF h and FFFE h ) is loaded into the PC ; therefore, program execution is possible from
any desired address. For example, when CO h and 3E h are stored at addresses FFFF h and FFFE h ,
respectively, the execution starts from address C03E h after reset.
The TLCS-870 Series utilizes pipelined processing (instruction pre-fetch); therefore, the PC always
indicates 2 addresses in advance. For example, while a 1-byte instruction stored at address Cl 23 h is being
executed, the PC contains Cl 25 h -
MSB LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PC Contents
Z)C
Program Counter (PC)
PC h PC l
Instruction Execution ХЗЗЕОСЗЕПС X a + 1
(a) Configuration
(b) Timing chart of PC contents and Instruction Execution
Figure 1-3. Program Counter
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24-8 2002
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