Jinüinjinjtjirlu^^ zeixixixdqc50, Jultljinnarij, Jinüinjinjtjirlu – Toshiba TMP87CP24AF User Manual
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TOSHIBA
TMP87CM24A/P24A
Count start
Count start
TCI pin input
Internal clock
Up-counter
TREG1B
INTTC1
i
Trigger
1
(INT2ES = 0)
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[Applications] High or low pulse width measurement
(a) Single Edge Capture
Count start
Count start
TCI pin input
Internal clock
Up-counter
TREG1B
INTTC1
I
1
I
(INT2ES = 0)
JUlTLJinnAriJ^^
Capture
X
Capture
X
À
[Applications] ® Period/Frequency measurement
® Duty measurement
(b) Double Edge Capture
Figure 2-20. Pulse Width Measurement Mode Timing Chart
(
6
)
Programmable Pulse Generate (PPG) output mode
Counting
is
started
by
an
edge
of
the
TCI
pin
input
(either
the
rising
or
falling
edge
can
be
selected)
or
by
a
command.
The
source
clock
is
used
an
internal
clock.
First,
the
contents
of
TREG1B
are
compared
with
the
contents
of
the
up-counter.
If
a
match
is
found,
timer
F/F1
output
is
toggled.
Next,
timer
F/F1
is
again
toggled
and
the
counter
is
cleared
by
matching
with
TREG1A.
An
INTTC1
interrupt
is
generated
at
this
time.
Timer
F/F
output
is
connected
to
the
P14
(PPG)
pin.
In the case of PPG output, set the P14 output latch to "1 " and configure as an output with PICR
4
.
Timer F/F1 is cleared to "0" during reset. The timer F/F1 value can also be set by program and either
a
positive
or
negative
logic
pulse
output
is
available.
Also,
writing
to
the
TREG1B
is
not
possible
unless the timer/counter 1 is set to the PPG output mode.
Example : "H" level 800
jus,
"L"" level 200
jus
pulse output at fc =
8
MHz
PI
4
output latch<-1
Sets PI 4 to an output mode
Sets PPG output mode
Sets a period (1 ms ^ 1 //S =
03E8
h
)
Sets "L" level pulse width (200 //S ^ 1
pis =
OOCB
h
)
Start
SET
(P1).4
LD
(P1CR),00010000B
LD
(TC1CR), 1000101 IB
LDW
(TREG1A), 03E8H
LDW
(TREG1B), 00C8H
LD
(TC1CR), 1001001 IB
3
-
24-72
2002
-
10-03