AMD Geode SC2200 User Manual
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AMD Geode™ SC2200 Processor Data Book
Core Logic Module - SMI Status and ACPI Registers - Function 1
32580B
1
THT_EN SMI Status. Indicates whether or not an SMI was caused by a write of 1 to the ACPI THT_EN bit (F1BAR1+I/O
Offset 00h[4]).
0: No.
1: Yes.
To enable SMI generation, set F1BAR1+I/O Offset 18h[8] to 1 (default).
0
SMI_CMD SMI Status. Indicates whether or not an SMI was caused by a write to the ACPI SMI_CMD register (F1BAR1+I/
O Offset 06h).
0: No.
1: Yes.
A write to the ACPI SMI_CMD register always generates an SMI.
Offset 24h-27h
External SMI Register (R/W)
Reset Value: 00000000h
Note:
EXT_SMI[7:0] are external SMIs, meaning external to the Core Logic module.
Bits [23:8] of this register contain second level of SMI status reporting. Top level status is reported in F1BAR0+I/O Offset 00h/
02h[10]. Reading bits [23:16] clears the second and top levels. If the value of the status bits must be read without clearing the
SMI source (and consequently de-asserting SMI), bits [15:8] can be read instead.
31:24
Reserved. Must be set to 0.
23
EXT_SMI7 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by assertion of EXT_SMI7.
0: No.
1: Yes.
To enable SMI generation, set bit 7 to 1.
22
EXT_SMI6 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI6.
0: No.
1: Yes.
To enable SMI generation, set bit 6 to 1.
21
EXT_SMI5 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI5.
0: No.
1: Yes.
To enable SMI generation, set bit 5 to 1.
20
EXT_SMI4 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI4.
0: No.
1: Yes.
To enable SMI generation, set bit 4 to 1.
19
EXT_SMI3 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI3.
0: No.
1: Yes.
To enable SMI generation, set bit 3 to 1.
18
EXT_SMI2 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI2.
0: No.
1: Yes.
To enable SMI generation, set bit 2 to 1.
17
EXT_SMI1 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI1.
0: No.
1: Yes.
To enable SMI generation, set bit 1 to 1.
16
EXT_SMI0 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI0.
0: No.
1: Yes.
To enable SMI generation, set bit 0 to 1.
Table 6-33. F1BAR0+I/O Offset: SMI Status Registers (Continued)
Bit
Description