Data port options menu, Data port options, Table a-4 – Paradyne 7112 User Manual
Page 84
Configuration Option Tables
A-8
7112-A2-GB20-10
March 1998
Data Port Options Menu
For Data Port Options, refer to Table A-4. To access the Data Port Options
screen, follow this menu selection sequence:
Main Menu
→
Configuration
→
Load Configuration From
→
Data Port
Table A-4.
Data Port Options (1 of 3)
Port Base Rate
Possible Settings: Nx56, Nx64
Default Setting: Nx64
Allows selection of the base rate for the synchronous data port. The data rate for the
port is a multiple (from 1 to 24) of the base rate specified with this configuration option.
Nx64 – Sets the base rate for this port to 64 kbps. The data rate is
Nx64 kbps, where N
is a number from 1 to 24.
Nx56 – Sets the base rate for this port to 56 kbps. The data rate is
Nx56 kbps, where N
is a number from 1 to 24.
Invert Transmit Clock
Possible Settings: Enable, Disable
Default Setting: Disable
Specifies whether the clock supplied by the DSU/CSU on the TXC interchange circuit
DB (CCITT 114) is phase inverted with respect to the Transmitted Data interchange
circuit BA (CCITT 103). This configuration option is useful when long cable lengths
between the DSU/CSU and the DTE are causing data errors.
Disable – Indicates TXC supplied by the DSU/CSU on this port is not phase inverted.
Enable – Indicates TXC supplied by the DSU/CSU on this port is phase inverted.
Transmit Clock Source
Possible Settings: Internal, External
Default Setting: Internal
Specifies whether the transmitted data for the synchronous data port is clocked using
an internal clock provided by the DSU/CSU (synchronized to the clock source specified
by the clock source configuration option) or an external clock provided by the DTE
connected to the synchronous data port. If an external clock is used, it must be
synchronized to the same clock source as the DSU/CSU.
Internal – Indicates the clock is provided internally by the DSU/CSU on the TXC
interchange circuit DB (CCITT 114).
External – Indicates the clock is provided externally by the DTE on the XTXC
interchange circuit DA (CCITT 113). Use this selection if the clock source is set to the
data port.