Intel PXA255 - Manual (Page 94)

3-32 Intel® PXA255 Processor Developer’s Manual
Clocks and Power Manager
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 3-16. PGSR0 Bit Definitions
0x40F0_0020 PGSR0 Clocks and Power Manager
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
31
SS
30
SS
29
SS
28
SS
27
SS
26
SS
25
SS
24
SS
23
SS
22
SS
21
SS
20
SS
19
SS
18
SS
17
SS
16
SS
15
SS
14
SS
13
SS
12
SS
11
SS
10
SS9 SS8 SS7 SS6 SS5 SS4 SS3 SS2 SS1 SS0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
[31:0] SSx
If programmed as an output, Sleep state of GPx
0 – Pin is driven to a zero during sleep mode
1 – Pin is driven to a one during sleep mode
Cleared by hardware, watchdog, and GPIO resets.
Table 3-17. PGSR1 Bit Definitions
0x40F0_0024 PGSR1 Clocks and Power Manager
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
63
SS
62
SS
61
SS
60
SS
59
SS
58
SS
57
SS
56
SS
55
SS
54
SS
53
SS
52
SS
51
SS
50
SS
49
SS
48
SS
47
SS
46
SS
45
SS
44
SS
43
SS
42
SS
41
SS
40
SS
39
SS
38
SS
37
SS
36
SS
35
SS
34
SS
33
SS
32
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
[31:0] SSx
If programmed as an output, Sleep state of GPx
0 – Pin is driven to a zero during sleep mode
1 – Pin is driven to a one during sleep mode
Cleared by hardware, watchdog, and GPIO resets.