Intel PXA255 - Manual (Page 328)

8-18 Intel® PXA255 Processor Developer’s Manual
Synchronous Serial Port Controller
8.7.4.2 Receive FIFO Not Empty Flag (RNE)
This non-interruptible bit is set when the receive FIFO contains one or more entries and is cleared
when the FIFO is empty. Because CPU interrupt requests are only made when the Receive FIFO
Threshold has been met or exceeded, the RNE bit can be polled when programmed I/O removes
remaining bytes of data from the receive FIFO. This bit does not request an interrupt.
8.7.4.3 SSP Busy Flag (BSY)
This is a non-interruptible read-only bit that is set when the SSP is actively transmitting and/or
receiving data and is cleared when the SSP is idle or disabled (SSE=0). This bit does not request an
interrupt. Since the software can read this bit before the SSP starts to transmit data, software must
read SSSP[TFL]=0x0 and SSSP[TNF]=0b1 and SSSP[BSY]=0b0 in order to insure that all data
has transmitted completely.
8.7.4.4 Transmit FIFO Service Request Flag (TFS)
This bit contains a maskable interrupt and is set when the transmit FIFO is nearly empty and
requires service to prevent an underrun. TFS is set any time the transmit FIFO has the same or
fewer valid data entries than indicated by the Transmit FIFO Threshold. It is cleared when it has
more valid data entries than the threshold value. When the TFS bit is set, an interrupt request is
made unless the transmit FIFO interrupt request enable (TIE) bit is cleared. The TFS bit’s setting
indicates whether a DMA service has been requested from the DMA controller. The DMA request
cannot be masked by the TIE bit. After the CPU or the DMA fills the FIFO such that it exceeds the
threshold, the TFS flag (and the service request and/or interrupt) is automatically cleared.
8.7.4.5 Receive FIFO Service Request Flag (RFS)
This bit contains a maskable interrupt and is set when the receive FIFO is nearly filled and requires
service to prevent an overrun. RFS is set any time the receive FIFO has the same or more valid data
entries than indicated by the Receive FIFO Threshold. It is cleared when it has fewer entries than
the threshold value. When the RFS bit is set, an interrupt request is made unless the receive FIFO
interrupt request enable (RIE) bit is cleared. The RFS bit’s setting indicates that DMA service has
been requested from the DMA controller. This DMA request cannot be masked by the RIE bit.
After the CPU or DMA reads the FIFO such that it has fewer entries than the RFT value, the RFS
flag (and the service request and/or interrupt) is automatically cleared.
8.7.4.6 Receiver Overrun Status (ROR)
This is a non-interruptible bit that is set when the receive logic attempts to place data into the
receive FIFO after it has been completely filled. Each time a new piece of data is received, the set
signal to the ROR bit is asserted and the newly received data is discarded. This process is repeated
for each new piece of data received until at least one empty FIFO entry exists. When the ROR bit is
set, an interrupt request that cannot be locally masked by any SSPC register bit is made to the CPU.
The ROR bit’s setting does not generate any DMA service request. Writing 0b1 to this bit resets
ROR status and its interrupt request. Writing a “0” does not affect ROR status.
8.7.4.7 Transmit FIFO Level (TFL)
This bit indicates the number of entries currently in the Transmit FIFO.