Intel PXA255 - Manual (Page 402)

11-16 Intel® PXA255 Processor Developer’s Manual
Fast Infrared Communication Port
11.4 FICP Register Summary
Table 11-8 shows the registers associated with the FICP block and the physical addresses used to
access them.
Table 11-8. FICP Register Summary
Address Name Description
0x4080_0000 ICCR0 FICP control register 0
0x4080_0004 ICCR1 FICP control register 1
0x4080_0008 ICCR2 FICP control register 2
0x4080_000C ICDR FICP data register
0x4080_0010 — reserved
0x4080_0014 ICSR0 FICP status register 0
0x4080_0018 ICSR1 FICP status register 1