8 receive fifo level (rfl), 8 ssp controller register summary, Ssp controller register summary -19 – Intel PXA255 User Manual
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Intel® PXA255 Processor Developer’s Manual
8-19
Synchronous Serial Port Controller
8.7.4.8
Receive FIFO Level (RFL)
This bit indicates the one less than number of entries in the Receive FIFO.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
8.8
SSP Controller Register Summary
shows the SSP registers associated with the SSP controller and their physical addresses.
Table 8-7. SSP Controller Register Summary
Address
Abbreviation
Full Name
0x4100_0000
SSCR0
SSP Control Register 0
0x4100_0004
SSCR1
SSP Control Register 1
0x4100_0008
SSSR
SSP Status Register
0x4100_000C
—
reserved
0x4100_0010
SSDR (Write / Read)
SSP Data Write Register/SSP Data Read Register