Intel PXA255 - Manual (Page 266)

7-2 Intel® PXA255 Processor Developer’s Manual
LCD Controller
In active color display mode, the LCD controller can drive TFT displays. When using 1-, 2-, 4-, or
8-bit modes, the LCD’s dither logic is bypassed, and the pixel value is sent from the palette buffer
directly to the LCD’s data output pins. 16-bit pixel mode bypasses both the palette and the dither
logic.
7.1.1 Features
The processor LCD controller supports the following features:
• Display modes:
— single- or dual-panel displays
— up to 256 gray-scale levels (8 bits) in Passive Monochrome Mode
— a total of 65536 possible colors in Passive Color Mode (using the 16-bit TMED dithering
algorithm)
— up to 65536 colors in Active Color Mode (16 bits, bypasses palette)
— passive 8-bit color single-panel displays
— passive 8-bit (per panel) color dual-panel displays
• Display sizes up to 1024x1024 pixels, recommended maximum of 640x480
• Internal color palette RAM 256 entry by 16 bits (can be loaded automatically at the beginning
of each frame)
• Encoded pixel data of 1, 2, 4, 8, or 16 bits
• Programmable toggle of AC bias pin output (toggled by line count)
• Programmable pixel clock from 195 kHz to 83 MHz (100 MHz/512 to 166 MHz/2)
• Integrated 2-channel DMA (one channel for palette and single panel, the other channel for
second panel in dual-panel mode).
• Programmable wait-state insertion at the beginning and end of each line
• Programmable polarity for output enable, frame clock, and line clock
• Programmable interrupts for input and output FIFO underrun
• Programmable frame and line clock polarity, pulse width, and wait counts