Intel PXA255 User Manual
Page 400
11-14
Intel® PXA255 Processor Developer’s Manual
Fast Infrared Communication Port
2
RAB
Receiver abort.
0 = No abort has been detected for the incoming frame.
1 = Abort detected during receipt of incoming frame. Two or more chips containing no
pulses or any invalid chips were detected on the receive pin. EOF bit set on last piece
of “good” data received before the abort, interrupt requested.
1
TUR
Transmit FIFO underrun.
0 – Transmit FIFO has not experienced an underrun.
1 – Transmit logic attempted to fetch data from transmit FIFO while it was empty. Interrupt
request signalled if not masked by ICCR0[TUS].
Underruns are not generated when the FICP transmitter is first enabled and is idle.
0
EIF
End/error in FIFO (read-only).
0 – Bits 8–10 are not set within any of the entries at or below the trigger level of the receive
FIFO. Receive FIFO DMA service requests are enabled.
1 – One or more tag bits (8 – 10) are set within the entries at or below the trigger level of
the receive FIFO. Request interrupt, disable receive FIFO DMA service requests.
This interrupt is not maskable in the FICP. Once the bad bytes have been removed from
the FIFO and EIF is cleared, DMA requests are automatically enabled.
Table 11-6. ICSR0 Bit Definitions (Sheet 2 of 2)
0x4080_0014
Fast Infrared Communication Port
Status Register 0 (ICSR0)
Fast Infrared Communication Port
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved
FR
E
RF
S
TFS
RA
B
TU
R
EIF
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description